应用笔记 (1)
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AN10704[AN10704]
数据手册 (1)
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LIN-I/O follower[UJA1023]
收到完整的详细信息。 请参阅 eCad 文件中的产品足迹等。
紧凑列表
LIN-I/O Follower
The UJA1023 is a stand-alone Local Interconnect Network (LIN) I/O follower that replaces basic components commonly used in electronic control units for input and output handling. The UJA1023 contains a LIN 2.0 controller, an integrated LIN transceiver which is LIN 2.0 / SAE J2602 compliant and LIN 1.3 compatible, a 30 kΩ termination resistor necessary for LIN-followers, and eight I/O ports which are configurable via the LIN bus.
An automatic bit rate synchronization circuit adapts to any (leader) bit rate between 1 kbit/s and 20 kbit/s. For this, an oscillator is integrated.
The LIN protocol will be handled autonomously and both Node Address (NAD) and LIN frame Identifier (ID) programming will be done by a leader request and an optional follower response message in combination with a daisy chain or plug coding function.
The eight bidirectional I/O pins are configurable via LIN bus messages and can have the following functions:
- Input:
- Standard input pin
- Local wake-up
- Edge capturing on falling, rising or both edges
- Analog input pin
- Switch matrix (in combination with output pins
- Output:
- Standard output pin as high-side driver, low-side driver or push-pull driver
- Cyclic sense mode for local wake-up
- PWM mode, for example, for back light illumination
- Switch matrix (in combination with input pins)
On entering a low-power mode it is possible to hold the last output state or to change over to a user programmable output state. In case of a failure (e.g. LIN bus short to ground) the output changes over to a user programmable limp home output state and the low-power Limp home mode will be entered.
Due to the advanced low-power behavior the power consumption of the UJA1023 in low-power mode is minimal.
SOT109-3 (SO16)
产品详情
Features
Key Features
- Automatic bit rate synchronization to any (leader) bit rate between 1 kbit/s and 20 kbit/s
- Integrated LIN 2.0 / SAE J2602 transceiver (including 30 kΩ termination resistor)
- Eight bidirectional I/O pins
- 4 x 2, 4 x 3, or 4 x 4 switch matrix to support reading and supplying a maximum number of 16 switches
- Outputs configurable as high-side and/or low-side driver and as cyclic or PWM driver
- 8-bit ADC
- Advanced low-power behavior
- On-chip oscillator
- Node Address (NAD) configuration via daisy chain or plug coding
- Inputs supporting local wake-up and edge capturing
- Configurable Sleep mode
- Limp home configuration in case of error conditions
- Very low electromagnetic emission
- High immunity against electromagnetic interference
- Bus line protected in accordance with ISO 7637
- Extended ambient temperature range (-40 Cel to +125 Cel)
购买/参数
1 结果
包含 0 不推荐用于新设计
部件 | 订购 | 计算机辅助设计模型 | 状态 | Recommended Orderable Part Number | 额外功能——模拟 | 产品类别 | 输入电压[最小到最大]（V） | 传输速率（最大）（Kbps） | Number of LIN Channels | 封装类型 |
|---|---|---|---|---|---|---|---|---|---|---|
正常供应 | UJA1023T/2R04/C,51 | 8x I/O - LIN configurable, ADC, Cyclic wake, HS/LS driver, INH, LIN 2.0, NAD, PWM, auto bit rate detection, limp home | LIN-I/O slave | 5.5 to 27 | 20.0 | 1 | SO16 |
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