LS1046AXE8T1A 产品信息|NXP

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技术

LS1046AXE8T1A

正常供应

LS1046AXE8T1A

正常供应
FBGA780, plastic, fine-pitch ball grid array; 780 bumps; 0.8 mm pitch; 23 mm x 23 mm x 2.46 mm body
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特点

Layerscape 64-bit Arm Cortex-A72, Quad-core, 1.8GHz, -40 to 105C, Security enabled

  • 数据手册:
  • PDF

封装

FBGA780: FBGA780, plastic, fine-pitch ball grid array; 780 bumps; 0.8 mm pitch; 23 mm x 23 mm x 2.46 mm body

购买选项

LS1046AXE8T1A

正常供应

12NC: 935338068557

详细信息

  • 包装: TRAY-Tray, Bakeable, Multiple in Drypack
  • 最小封装数量: 60
  • 起订量: 60
  • 交付周期: 18 weeks
  • 预算报价（不含税）: 100 在 US$103.11 USD

订购

从分销商处购买

工作特点

参数值
Core: Number of cores (SPEC)
4
Core Type
Arm Cortex-A72
Operating Frequency [Max] (MHz)
1800
External Memory Supported
DDR4 SDRAM
SRAM (kB)
128
Cache (KB)
32, 48
参数值
UART
10
SPI
1
I2C
4
USB Controllers
3
Ethernet
26

环境

部件/12NC无铅欧盟 RoHS无卤素RHF指标二级互连REACH SVHC重量（mg）
LS1046AXE8T1A(935338068557)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
D
e1
REACH SVHC
3960.1

质量

部件/12NC安全保障功能安全湿度灵敏度等级(MSL)封装体峰值温度（PPT）（C°）Maximum Time at Peak Temperatures (s)
无铅焊接无铅焊接无铅焊接
LS1046AXE8T1A
(935338068557)
No
3
250
30

配送

部件/12NC协调关税 (美国)免责声明出口控制分类编号 (美国)CCATS
LS1046AXE8T1A
(935338068557)
854231
5A002A1
G165493

产品变更通知

部件/12NC发行日期生效日期产品更改通知标题
LS1046AXE8T1A
(935338068557)
2025-04-162025-05-26202504006IFreescale Logo to NXP Logo Product Marking Conversion for All Remaining Former Freescale Products
LS1046AXE8T1A
(935338068557)
2020-12-152020-12-16202011011INXP Will Add a Sealed Date to the Product Label

更多信息 LS1046A

The LS1046A and LS1026A processors integrate quad and dual 64-bit Arm® Cortex®-A72 cores respectively with packet processing acceleration and high-speed peripherals. They are pin-compatible with LS1023A, LS1043A and LS1088A SoC to provide performance scaling for 64-bit Arm, ranging from dual-A53 through octal-A53 to quad-A72 core processors, while maintaining hardware and software compatibility.

Layerscape processors are part of NXP's EdgeVerse™ edge computing platform.

Both devices are proven certifiable to the Arm SystemReady ES  standard to ensure interoperability with standard operating systems and hypervisors.