PCA9617ATP 产品信息|NXP

PCA9617ATP

正常供应

PCA9617ATP

正常供应

购买选项

PCA9617ATPZ

正常供应

12NC: 935299954147

详细信息

工作特点

参数
Inputs
1
Outputs
1
Type Of Offset
Static Offset
参数
Supply Voltage [Min to Max] (V)
0.8 to 5.5, 2.2 to 5.5
Frequency (Max) (MHz)
1
Operating Temperature (Min-Max) (℃)
-40 to 85

环境

部件/12NC无铅欧盟 RoHS无卤素RHF指标REACH SVHC重量(mg)
PCA9617ATPZ(935299954147)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
DREACH SVHC
12.03003

质量

部件/12NC安全保障功能安全湿度灵敏度等级(MSL)封装体峰值温度(PPT)(C°)
铅焊接无铅焊接铅焊接无铅焊接
PCA9617ATPZ
(935299954147)
No
1
1
240
260

配送

部件/12NC协调关税 (美国)免责声明
PCA9617ATPZ
(935299954147)
854239

更多信息 PCA9617A

The PCA9617A is a CMOS integrated circuit that provides level shifting between low voltage (0.8 V to 5.5 V) and higher voltage (2.2 V to 5.5 V) Fast-mode Plus (Fm+) I²C-bus or SMBus applications. While retaining all the operating modes and features of the I²C-bus system during the level shifts, it also permits extension of the I²C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds. Using the PCA9617A enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PCA9617A is unpowered.

The 2.2 V to 5.5 V bus port B drivers have the static level offset, while the adjustable voltage bus port A drivers eliminate the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V LOW on the port A which accommodates the smaller voltage swings of lower voltage logic.

The static offset design of the port B PCA9617A I/O drivers prevents them from being connected to the static or incremented offset of other bus buffers. Port A of two or more PCA9617As can be connected together, however, to allow a star topography with port A on the common bus, and port A can be connected directly to any other buffer with static or incremented offset outputs. Multiple PCA9617As can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays to consider.

The PCA9617A drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above 2.2 V. The EN pin is referenced to VCC(B) and can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the enable pin when the bus is idle.

The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V, while the input threshold of the internal buffer is set about 90 mV lower (0.45 V). When the port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a latching condition from occurring. The output pull-down on port A drives a hard LOW and the input level is set at 0.35 VCC(A) to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is as low as 0.8 V.