Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
特点
QorIQ, 64-Bit Power Arch SoC, 2 X 1.6GHz, DDR3, PCIe, GbE, SRIO, HW Accel, -40 to 105C R2.0
购买选项
P5020NXN7QMB
使用寿命终止
12NC: 935317947557
详细信息
订购
工作特点
| 参数 | 值 |
|---|---|
Core Type | e5500 |
Core: Number of cores (SPEC) | 2 |
Operating Frequency [Max] (MHz) | 1600 |
| 参数 | 值 |
|---|---|
PCIe | 4 |
External Memory Supported | DDR3 SDRAM, DDR3L SDRAM |
环境
| 部件/12NC | 无铅 | 欧盟 RoHS | 无卤素 | RHF指标 | 二级互连 | REACH SVHC | 重量（mg） |
|---|---|---|---|---|---|---|---|
P5020NXN7QMB(935317947557) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | e1 | REACH SVHC | 13973.9 |
质量
| 部件/12NC | 安全保障功能安全 | 湿度灵敏度等级(MSL) | 封装体峰值温度（PPT）（C°） | Maximum Time at Peak Temperatures (s) | |||
|---|---|---|---|---|---|---|---|
| 无铅焊接 | 无铅焊接 | 无铅焊接 | |||||
P5020NXN7QMB (935317947557) | No | 3 | 245 | 30 | |||
配送
| 部件/12NC | 协调关税 (美国)免责声明 | 出口控制分类编号 (美国) |
|---|---|---|
P5020NXN7QMB (935317947557) | 854231 | 3A991A1 |
停产和更换部件数据
| 部件/12NC | 停产通知 | 上次购买日期 | 上次发货日期 | 替代器件 |
|---|---|---|---|---|
P5020NXN7QMB (935317947557) | NOTICE | 2020-03-30 | 2020-09-30 | - |
产品变更通知
| 部件/12NC | 发行日期 | 生效日期 | 产品更改通知 | 标题 |
|---|---|---|---|---|
P5020NXN7QMB (935317947557) | 2025-04-16 | 2025-05-26 | 202504008I | Freescale Logo to NXP Logo Product Marking Conversion for All Remaining Former Freescale Products |
P5020NXN7QMB (935317947557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
P5020NXN7QMB (935317947557) | 2019-09-25 | 2019-09-26 | 201909022DN | Discontinuance Notice for DSP56303 68360 PBGA only 8569 P5020 8272 Family Lead only 8313 Family Lead only |
更多信息 P5020
The dual-core P5020 and single-core P5010 processors deliver 64-bit processing, based on the e5500 core built on Power Architecture® technology. With frequencies scalable to 2.0 GHz, large caches and high per-cycle efficiency, these products target control plane and computer applications that require high single-threaded performance.
The P5 platform leverages architectural features pioneered in the P4 platform, including the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet® switch fabric that eliminates internal bottlenecks. This enables architectural compatibility from the P5 platform to the P4 platform as well as to the P3 platform.