QorIQ® P5020 | NXP 半导体

安全互联汽车

工业

消费电子

技术

QorIQ® P5020和P5010 64位单核和双核通信处理器

P5020
停产
QorIQ<sup>&#174;</sup> P5020/P5010 - Product Introduction

点击播放视频

双核P5020和单核P5010处理器是基于Power Architecture®技术，采用e5500内核的64位处理器。频率范围可扩展到2.0GHz，具有缓存容量大、单周期效率高等特点，适用于控制平台和需要较高单线程性能的计算应用。

P5平台沿袭了P4平台先进的架构特性，包括可降低延迟的三级缓存，提供可靠的虚拟化支持的硬件管理程序，减轻内核数据包处理负担的数据通路加速架构(DPAA)，以及消除内部瓶颈的CoreNet®交换结构。P5平台与P4平台以及P3平台架构兼容。

框图

P5020 BD

QorIQ P5020/10 64-bit Single- and Dual-Core Communications Processors
获取框图PDF

特征

内核复合体

  • 单或双64位e5500内核，运行频率为2.0 GHz
  • 三级缓存：32 KB I/D L1；每内核512 KB专用L2；2MB共享L3
  • 运行频率最高达2.0 GHz，支持64位ISA (符合Power Architecture v2.06)
  • 指令有3个等级：用户、超级用户、管理程序
  • 混合32位模式，支持原有软件，并可向64位架构平稳过渡
  • 2.0 MB配置为双1 MB平台缓存

网络元件

  • SerDes
    • 18个通道，高达5 Gbps
    • 支持SGMII，串行RapidIO®，XAUI，PCI Express® (PCIe)修订版1.1/2.0，SATA
  • 以太网接口
    • 10 Gbps以太网MAC
    • 5个1 Gbps以太网MAC

加速器和存储器控制

  • 两个64位DDR3/3L SDRAM存储器控制器，支持ECC和交错存取功能
    • 高达1300MT/S
  • 帧管理器，用于数据包处理
  • 队列管理器，用于监控、调度和分配工作负载
  • 安全模块，进行加密算法加速
  • RAID5/6，用于存储应用奇偶计算
  • RapidIO®消息管理器，用于9和11类消息传送
  • 模式匹配引擎，用于正则表达式搜索

基本外设和互连

  • 多达4个PCIe 2.0/3.0控制器
  • 两个串行ATA (SATA 2.0)控制器
  • 两个USB 2.0控制器，带有集成PHY
  • 增强型安全数字主机控制器(SD/MMC/eMMC)
  • 两个I²C控制器
  • 两个DUART

其他特性

  • 硬件管理程序，在内核之间进行安全的操作系统分区
  • 可信引导功能，确保只有正确的代码被引导，且代码不能反向工程
  • 本产品包含在恩智浦产品长期供货计划中， 自推出后至少保证10年供货

更多

对比表

对照表

P5020 P5010
内核 2 1
内核频率 1.6至2.0 GHz 1.6至2.0 GHz
L2缓存 512 KB 512 KB
L3/平台缓存 2 MB 1 MB
DDR3 2x 64位 1x 64位
GbE 5x 1 GbE，1x 10 GbE 5x 1 GbE，1x 10 GbE
SERDES 18通道 18通道
安全性 可信 可信

购买/参数

‌
‌
‌
‌
‌
‌
‌
‌
‌
‌
‌
‌
‌
‌
‌
‌
‌

‌
‌
‌
‌
‌
‌
‌
‌

‌
‌
‌
‌
‌
‌
‌
‌

‌
‌
‌
‌
‌
‌
‌
‌

‌
‌
‌
‌
‌
‌
‌
‌

‌
‌
‌
‌
‌
‌
‌
‌

‌
‌
‌
‌
‌
‌
‌
‌

‌
‌
‌
‌
‌
‌
‌
‌

‌
‌
‌
‌
‌
‌
‌
‌

‌
‌
‌
‌
‌
‌
‌
‌

‌
‌
‌
‌
‌
‌
N true 0 PSPP5020zh 39 产品简介 Product Brief t532 1 参考手册 Reference Manual t877 5 应用笔记 Application Note t789 19 应用笔记软件 Application Note Software t783 1 手册 Brochure t518 2 支持信息 Supporting Information t531 2 数据手册 Data Sheet t520 1 白皮书 White Paper t530 6 简介 Fact Sheet t523 2 zh 4 1 1 English The QorIQ<sup>&#174;</sup> P5020DS is a flexible development system based on the dual-core 32/64-bit moded P5020 device. The board, with its 2.0 GHz P5020 and rich I/O mix, is intended for evaluation of the QorIQ P5020/P5010 processor in networking, telecom and industrial applications, where its highperformance, high-efficiency core and integration make it very well suited as a control plane processor. 1316723002854716246902 PSP 243.5 KB None None documents None 1316723002854716246902 /docs/en/fact-sheet/P5020DSFS.pdf 243469 /docs/en/fact-sheet/P5020DSFS.pdf P5020DSFS N N 2016-10-31 QorIQ P5020 Development System Fact Sheet /docs/en/fact-sheet/P5020DSFS.pdf /docs/en/fact-sheet/P5020DSFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Mar 11, 2013 Fact Sheet t523 简介 Fact Sheet Y N QorIQ P5020 Development System Fact Sheet 2 1 English The new QorIQ<sup>&#174;</sup> P2040/P2041 and P3041 processors expand the reach of NXP&#8217;s P4 platform into lower power applications. The P2040/P2041 and P3041 processors integrate four e500mc cores based on Power Architecture technology running up to 1.5 GHz within 12 watts. The new P5020 and P5010 processors offer NXP&#8217;s highest single-threaded performance for next-generation embedded control plane applications. With frequencies scaling to 2.2 GHz. 1316699641906701481590 PSP 758.9 KB None None documents None 1316699641906701481590 /docs/en/brochure/P2P3P5APPBRF.pdf 758908 /docs/en/brochure/P2P3P5APPBRF.pdf P2P3P5APPBRF N N 2016-10-31 QorIQ P2040/P2041, P3 and P5 Series - Brochures /docs/en/brochure/P2P3P5APPBRF.pdf /docs/en/brochure/P2P3P5APPBRF.pdf Brochure N Y 712453003803778552 2022-12-07 pdf N en Sep 14, 2012 Brochure t518 手册 Brochure N QorIQ P2040/P2041, P3 and P5 Series - Brochures 3 1 English Security continues to be an increasingly important concern in the design of modern systems. Threats against networks and network-connected&#13;&#10;devices are real and growing. With an estimated $40 billion (USD)* of data loss per year, service providers and end-users are becoming painfully&#13;&#10;aware of the consequences of unsecured networks and databases. 1317136062337713598350 PSP 494.4 KB None None documents None 1317136062337713598350 /docs/en/white-paper/QORIQSECBOOTWP.pdf 494394 /docs/en/white-paper/QORIQSECBOOTWP.pdf QORIQSECBOOTWP N N 2016-10-31 Secure Boot - White Paper /docs/en/white-paper/QORIQSECBOOTWP.pdf /docs/en/white-paper/QORIQSECBOOTWP.pdf White Paper N Y 918633085541740938 2023-06-19 pdf N en Jan 25, 2013 White Paper t530 白皮书 White Paper N Secure Boot - White Paper 4 6 English The QorIQ<sup>&#174;</sup> P5 family delivers scalable 64-bit processing with single-, dual- and quad-core devices. With frequencies scaling up to 2.0 GHz, a tightly coupled cache hierarchy for low latency and integrated hardware acceleration, the P5020 (dual-core) and P5010 (single-core) devices are ideally suited for compute intensive, power-conscious control plane applications. 1275057777362722058756 PSP 130.8 KB None None documents None 1275057777362722058756 /docs/en/fact-sheet/QP5020FS.pdf 130794 /docs/en/fact-sheet/QP5020FS.pdf QP5020FS N N 2010-06-14 QorIQ<sup>&#174;</sup> P5020/P5010 Communications Processors - Fact Sheet /docs/en/fact-sheet/QP5020FS.pdf /docs/en/fact-sheet/QP5020FS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Apr 23, 2014 Fact Sheet t523 简介 Fact Sheet Y N QorIQ<sup>&#174;</sup> P5020/P5010 Communications Processors - Fact Sheet false zh zh 数据手册 Data Sheet 1 5 1 English The P5020 and P5010 QorIQ<sup>&#174;</sup> integrated communication processor combines Power Architecture&#174; processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications. 1363723529239706397087 PSP 3.1 MB Registration without Disclaimer None documents Extended 1363723529239706397087 /secured/assets/documents/en/data-sheet/P5020EC.pdf 3078934 /secured/assets/documents/en/data-sheet/P5020EC.pdf P5020EC documents Y N 2013-03-19 P5020/P5010 QorIQ<sup>&#174;</sup> Integrated Processor Hardware Specifications - Data Sheet /webapp/Download?colCode=P5020EC&lang_cd=zh /secured/assets/documents/en/data-sheet/P5020EC.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Mar 2, 2015 980000996212993340 Data Sheet Y N P5020/P5010 QorIQ<sup>&#174;</sup> Integrated Processor Hardware Specifications - Data Sheet 参考手册 Reference Manual 5 6 5 English This document describes the functionality of the P5020 QorIQ<sup>&#174;</sup> chip. 1320689046404720689946 PSP 18.3 MB Registration without Disclaimer None documents Extended 1320689046404720689946 /secured/assets/documents/en/reference-manual/P5020RM.pdf 18287305 /secured/assets/documents/en/reference-manual/P5020RM.pdf P5020RM documents Y N 2011-11-07 P5020 QorIQ<sup>&#174;</sup> Integrated Multicore Communication Processor Family Reference Manual with Updates - Reference Manual /webapp/Download?colCode=P5020RM&lang_cd=zh /secured/assets/documents/en/reference-manual/P5020RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 11, 2016 500633505221135046 Reference Manual Y N P5020 QorIQ<sup>&#174;</sup> Integrated Multicore Communication Processor Family Reference Manual with Updates - Reference Manual 7 4 English e5500RM: This document includes the register model, instruction model, MMU, memory subsystem, debug and performance monitor facilities of the e5500. 1320675592951722488289 PSP 3.7 MB Registration without Disclaimer None documents Extended 1320675592951722488289 /secured/assets/documents/en/reference-manual/e5500RM.pdf 3661467 /secured/assets/documents/en/reference-manual/e5500RM.pdf E5500RM documents Y N 2011-11-07 e5500RM, e5500 Core Reference Manual with Updates - Reference Manual /webapp/Download?colCode=E5500RM&lang_cd=zh /secured/assets/documents/en/reference-manual/e5500RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 28, 2015 500633505221135046 Reference Manual Y N e5500RM, e5500 Core Reference Manual with Updates - Reference Manual 8 1 English This reference manual describes the resources defined for the Power ISA embedded environment. 1319210247754725815434 PSP 10.4 MB Registration without Disclaimer None documents Extended 1319210247754725815434 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 10448185 /secured/assets/documents/en/reference-manual/EREF_RM.pdf EREF_RM documents Y N 2016-10-31 EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /webapp/Download?colCode=EREF_RM&lang_cd=zh /secured/assets/documents/en/reference-manual/EREF_RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 26, 2014 500633505221135046 Reference Manual Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 9 2 English This manual describes the core set of DPAA functionality implemented in many QorIQ<sup>&#174;</sup> chips, and identifies those portions of the DPAA whose implementation varies from chip to chip. 1301610099994679235703 PSP 19.4 MB Registration without Disclaimer None documents Extended 1301610099994679235703 /secured/assets/documents/en/reference-manual/DPAARM.pdf 19426366 /secured/assets/documents/en/reference-manual/DPAARM.pdf DPAARM documents Y N 2016-10-31 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual /webapp/Download?colCode=DPAARM&lang_cd=zh /secured/assets/documents/en/reference-manual/DPAARM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Nov 4, 2011 500633505221135046 Reference Manual Y N QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual 10 0 English 1319838154290711097752 PSP 4.7 MB Registration without Disclaimer None documents Extended 1319838154290711097752 /secured/assets/documents/en/reference-manual/P5020SECRM.pdf 4696534 /secured/assets/documents/en/reference-manual/P5020SECRM.pdf P5020SECRM documents Y N 2011-10-28 P5020 Security (SEC 4.2) Reference Manual /webapp/Download?colCode=P5020SECRM&lang_cd=zh /secured/assets/documents/en/reference-manual/P5020SECRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Oct 28, 2011 500633505221135046 Reference Manual Y N P5020 Security (SEC 4.2) Reference Manual 应用笔记 Application Note 19 11 0 English AN5295: This application note outlines some common bring-up issues that customers may face when using the Serial RapidIO (SRIO) protocol on NXP QorIQ<sup>&#174;</sup> devices. The document covers issues related to device errata, hardware design, and software or configuration that may affect SRIO operation or performance. These guidelines aim to help with debugging problems and speed up the bring-up process. 1464124094029726989039 PSP 401.8 KB None None documents None 1464124094029726989039 /docs/en/application-note/AN5295.pdf 401764 /docs/en/application-note/AN5295.pdf AN5295 documents N N 2016-10-31 AN5295, QorIQ Serial RapidIO Debug Tips - Application Note /docs/en/application-note/AN5295.pdf /docs/en/application-note/AN5295.pdf Application Note N 645036621402383989 2022-12-07 pdf N en May 24, 2016 645036621402383989 Application Note N AN5295, QorIQ Serial RapidIO Debug Tips - Application Note 12 1 English AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105 PSP 1.0 MB None None documents None 1456317293250700197105 /docs/en/application-note/AN5260.pdf 1027928 /docs/en/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf /docs/en/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 en Nov 30, 2020 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 0 Chinese AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105zh PSP 1.0 MB None None documents None 1456317293250700197105 /docs/zh/application-note/AN5260.pdf 1027928 /docs/zh/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf /docs/zh/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 pdf N zh Feb 24, 2016 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 13 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 14 4 English AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. 1264810112254717714233 PSP 468.7 KB None None documents None 1264810112254717714233 /docs/en/application-note/AN4039.pdf 468655 /docs/en/application-note/AN4039.pdf AN4039 documents N N 2016-10-31 AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf /docs/en/application-note/AN4039.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 11, 2014 645036621402383989 Application Note N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 15 0 English AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. 1390372586014711432307 PSP 1.2 MB Registration without Disclaimer None documents Extended 1390372586014711432307 /secured/assets/documents/en/application-note/AN4848.pdf 1207848 /secured/assets/documents/en/application-note/AN4848.pdf AN4848 documents Y N 2016-10-31 AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /webapp/Download?colCode=AN4848&lang_cd=zh /secured/assets/documents/en/application-note/AN4848.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Jan 21, 2014 645036621402383989 Application Note N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 16 2 English This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. 1363012931515701443659 PSP 269.4 KB None None documents None 1363012931515701443659 /docs/en/application-note/AN4531.pdf 269380 /docs/en/application-note/AN4531.pdf AN4531 documents N N 2016-10-31 AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf /docs/en/application-note/AN4531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 16, 2013 645036621402383989 Application Note N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 17 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940&lang_cd=zh /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 18 1 English This document describes how to calculate the maximum frequency and transfer formats and includes eSPI programming examples. 1329517560294722281831 PSP 216.6 KB None None documents None 1329517560294722281831 /docs/en/application-note/AN4375.pdf 216552 /docs/en/application-note/AN4375.pdf AN4375 documents N N 2016-10-31 QorIQ eSPI Controller Register Setting Considerations and Programming Examples /docs/en/application-note/AN4375.pdf /docs/en/application-note/AN4375.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jun 21, 2012 645036621402383989 Application Note N QorIQ eSPI Controller Register Setting Considerations and Programming Examples 19 0 English This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. 1309961595210675753552 PSP 743.2 KB None None documents None 1309961595210675753552 /docs/en/application-note/AN4326.pdf 743199 /docs/en/application-note/AN4326.pdf AN4326 documents N 2016-10-31 Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf /docs/en/application-note/AN4326.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jul 6, 2011 645036621402383989 Application Note N Verification of the IEEE 1588 Interface 20 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311&lang_cd=zh /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 21 0 English This document describes how to initialize and configure some of the individual elements of the DPAA to send packets in and out of the device. 1301697264409722558859 PSP 648.7 KB Registration without Disclaimer None documents Extended 1301697264409722558859 /secured/assets/documents/en/application-note/AN4290.pdf 648695 /secured/assets/documents/en/application-note/AN4290.pdf AN4290 documents Y N 2016-10-31 Configuring the Data Path Acceleration Architecture (DPAA) /webapp/Download?colCode=AN4290&lang_cd=zh /secured/assets/documents/en/application-note/AN4290.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 1, 2011 645036621402383989 Application Note N Configuring the Data Path Acceleration Architecture (DPAA) 22 0 English 1287581868481730872047 PSP 142.0 KB None None documents None 1287581868481730872047 /docs/en/application-note/AN3423.pdf 141965 /docs/en/application-note/AN3423.pdf AN3423 documents N 2016-10-31 Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors /docs/en/application-note/AN3423.pdf /docs/en/application-note/AN3423.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 6, 2010 645036621402383989 Application Note N Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors 23 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939&lang_cd=zh /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 24 0 English AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. 1269842191514722596708 PSP 576.8 KB None None documents None 1269842191514722596708 /docs/en/application-note/AN4064.pdf 576818 /docs/en/application-note/AN4064.pdf AN4064 documents N 2016-10-31 AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf /docs/en/application-note/AN4064.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 28, 2010 645036621402383989 Application Note N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 25 1 English This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. 1264143083962735811350 PSP 514.4 KB None None documents None 1264143083962735811350 /docs/en/application-note/AN4056.pdf 514364 /docs/en/application-note/AN4056.pdf AN4056 documents N 2016-10-31 Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf /docs/en/application-note/AN4056.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 18, 2010 645036621402383989 Application Note N Understanding SYSCLK Jitter 26 2 English NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. 1213738938672737755656 PSP 495.3 KB None None documents None 1213738938672737755656 /docs/en/application-note/AN3638.pdf 495318 /docs/en/application-note/AN3638.pdf AN3638 documents N N 2016-10-31 The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf /docs/en/application-note/AN3638.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 26, 2009 645036621402383989 Application Note N The SystemID Format for Power Architecture™ Development Systems 27 0 English This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. 1244236817778728476903 PSP 692.4 KB Registration without Disclaimer None documents Extended 1244236817778728476903 /secured/assets/documents/en/application-note/AN3869.pdf 692438 /secured/assets/documents/en/application-note/AN3869.pdf AN3869 documents Y N 2016-10-31 Implementing SGMII Interfaces on the PowerQUICC™ III /webapp/Download?colCode=AN3869&lang_cd=zh /secured/assets/documents/en/application-note/AN3869.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 5, 2009 645036621402383989 Application Note N Implementing SGMII Interfaces on the PowerQUICC™ III 28 0 English This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. 1196228463425717224884 PSP 573.0 KB None None documents None 1196228463425717224884 /docs/en/application-note/AN3532.pdf 572952 /docs/en/application-note/AN3532.pdf AN3532 documents N 2016-10-31 Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf /docs/en/application-note/AN3532.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 27, 2007 645036621402383989 Application Note N Error Correction and Error Handling on PowerQUICC (TM) III Processors 29 2 English These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. 1128961595061725581551 PSP 619.7 KB None None documents None 1128961595061725581551 /docs/en/application-note/AN2910.pdf 619650 /docs/en/application-note/AN2910.pdf AN2910 documents N 2016-10-31 Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf /docs/en/application-note/AN2910.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 27, 2007 645036621402383989 Application Note N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 应用笔记软件 Application Note Software 1 30 0 English This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. 1181767584945705509512 PSP 163.7 KB None None documents None 1181767584945705509512 /docs/en/application-note-software/AN3372.pdf 163681 /docs/en/application-note-software/AN3372.pdf AN3372 documents N 2016-10-31 Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf /docs/en/application-note-software/AN3372.pdf Application Note Software N 789425793691620447 2022-12-07 pdf en Jun 13, 2007 789425793691620447 Application Note Software N Challenges in Testing for Power Rail Shorts with New Technologies 手册 Brochure 1 31 0 English 1326753923169722820717 PSP 477.8 KB None None documents None 1326753923169722820717 /docs/en/brochure/PWRARBYNDBITSTA.pdf 477805 /docs/en/brochure/PWRARBYNDBITSTA.pdf PWRARBYNDBITSTA documents N 2016-10-31 Trust Architecture: Freescale’s Security Solution for Industrial Control Systems (ICS) /docs/en/brochure/PWRARBYNDBITSTA.pdf /docs/en/brochure/PWRARBYNDBITSTA.pdf Brochure N 712453003803778552 2022-12-07 pdf en Feb 7, 2012 712453003803778552 Brochure N Trust Architecture: Freescale’s Security Solution for Industrial Control Systems (ICS) 产品简介 Product Brief 1 32 1 English This document provides an overview of the P5020 QorIQ<sup>&#174;</sup> communications processor features as well as application use cases. 1323291061302702296154 PSP 232.5 KB None None documents None 1323291061302702296154 /docs/en/product-brief/P5020PB.pdf 232482 /docs/en/product-brief/P5020PB.pdf P5020PB documents N N 2011-12-07 P5020 QorIQ<sup>&#174;</sup> Communications Processor Product Brief /docs/en/product-brief/P5020PB.pdf /docs/en/product-brief/P5020PB.pdf Product Brief N 899114358132306053 2022-12-07 pdf N en Feb 13, 2013 899114358132306053 Product Brief Y N P5020 QorIQ<sup>&#174;</sup> Communications Processor Product Brief 支持信息 Supporting Information 2 33 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 34 0 English 1292347733521725919077 PSP 22.8 KB None None documents None 1292347733521725919077 /docs/en/supporting-information/P5020_P5010PECI.pdf 22834 /docs/en/supporting-information/P5020_P5010PECI.pdf P5020_P5010PECI documents N N 2016-10-31 P5020_P5010 Family Customer Export Control Information /docs/en/supporting-information/P5020_P5010PECI.pdf /docs/en/supporting-information/P5020_P5010PECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Dec 10, 2010 371282830530968666 Supporting Information Y N P5020_P5010 Family Customer Export Control Information 白皮书 White Paper 5 35 0 English QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. 1419964678458711207150 PSP 1.4 MB None None documents None 1419964678458711207150 /docs/en/white-paper/QORIQPMWP.pdf 1418055 /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP documents N N 2017-03-30 QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf /docs/en/white-paper/QORIQPMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Mar 30, 2017 918633085541740938 White Paper N QORIQPMWP, QorIQ Power Management - White Paper 36 0 English This white paper demonstrates how to best architect software to leverage the DPAA hardware. 1338565191762730130183 PSP 1.1 MB None None documents None 1338565191762730130183 /docs/en/white-paper/QORIQDPAAWP.pdf 1051628 /docs/en/white-paper/QORIQDPAAWP.pdf QORIQDPAAWP documents N N 2016-10-31 QorIQ DPAA Primer for Software Architecture /docs/en/white-paper/QORIQDPAAWP.pdf /docs/en/white-paper/QORIQDPAAWP.pdf White Paper N 918633085541740938 2022-12-07 pdf N en Jun 1, 2012 918633085541740938 White Paper Y N QorIQ DPAA Primer for Software Architecture 37 2 English This paper discusses the objectives of the trust architecture, how it works, and logistical considerations. 1283981132878727112937 PSP 650.6 KB Registration without Disclaimer None documents Extended 1283981132878727112937 /secured/assets/documents/en/white-paper/QORIQTAWP.pdf 650609 /secured/assets/documents/en/white-paper/QORIQTAWP.pdf QORIQTAWP documents Y N 2016-10-31 An Introduction to the QorIQ Platform's Trust Architecture /webapp/Download?colCode=QORIQTAWP&lang_cd=zh /secured/assets/documents/en/white-paper/QORIQTAWP.pdf White Paper N 918633085541740938 2022-12-07 pdf Y en May 10, 2011 918633085541740938 White Paper Y N An Introduction to the QorIQ Platform's Trust Architecture 38 0 English CritialBlue&#13;&#10;&#13;&#10;Prism software 1289917463417712987902 PSP 673.1 KB None None documents None 1289917463417712987902 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf 673125 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf LTEWHTPPRCRTBLA4 documents N 2016-10-31 Tuning QorIQ Processor Performance /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf White Paper N 918633085541740938 2022-12-07 pdf en Nov 16, 2010 918633085541740938 White Paper N Tuning QorIQ Processor Performance 39 0 English The new NXP e5500 core is the latest technology evolution in the QorIQ<sup>&#174;</sup> family of communications platforms, enabling applications to take advantage of 64 bits of data per clock cycle. 1276778683844715153792 PSP 227.0 KB None None documents None 1276778683844715153792 /docs/en/white-paper/64BTTCHNLGYWP.pdf 227035 /docs/en/white-paper/64BTTCHNLGYWP.pdf 64BTTCHNLGYWP documents N 2010-06-22 Introducing the e5500 Core /docs/en/white-paper/64BTTCHNLGYWP.pdf /docs/en/white-paper/64BTTCHNLGYWP.pdf White Paper N 918633085541740938 2022-12-07 pdf en Jun 16, 2010 918633085541740938 White Paper Y N Introducing the e5500 Core false 0 P5020 downloads zh-Hans true 1 Y PSP 产品简介 1 /docs/en/product-brief/P5020PB.pdf 2011-12-07 1323291061302702296154 PSP 32 Feb 13, 2013 Product Brief This document provides an overview of the P5020 QorIQ<sup>&#174;</sup> communications processor features as well as application use cases. None /docs/en/product-brief/P5020PB.pdf English documents 232482 None 899114358132306053 2022-12-07 N /docs/en/product-brief/P5020PB.pdf P5020 QorIQ<sup>&#174;</sup> Communications Processor Product Brief /docs/en/product-brief/P5020PB.pdf documents 899114358132306053 Product Brief N en None Y pdf 1 N N P5020 QorIQ<sup>&#174;</sup> Communications Processor Product Brief 232.5 KB P5020PB N 1323291061302702296154 参考手册 5 /secured/assets/documents/en/reference-manual/P5020RM.pdf 2011-11-07 1320689046404720689946 PSP 6 Jul 11, 2016 Reference Manual This document describes the functionality of the P5020 QorIQ<sup>&#174;</sup> chip. Registration without Disclaimer /secured/assets/documents/en/reference-manual/P5020RM.pdf English documents 18287305 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=P5020RM&lang_cd=zh P5020 QorIQ<sup>&#174;</sup> Integrated Multicore Communication Processor Family Reference Manual with Updates - Reference Manual /secured/assets/documents/en/reference-manual/P5020RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 5 Y N P5020 QorIQ<sup>&#174;</sup> Integrated Multicore Communication Processor Family Reference Manual with Updates - Reference Manual 18.3 MB P5020RM N 1320689046404720689946 /secured/assets/documents/en/reference-manual/e5500RM.pdf 2011-11-07 1320675592951722488289 PSP 7 Jul 28, 2015 Reference Manual e5500RM: This document includes the register model, instruction model, MMU, memory subsystem, debug and performance monitor facilities of the e5500. Registration without Disclaimer /secured/assets/documents/en/reference-manual/e5500RM.pdf English documents 3661467 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=E5500RM&lang_cd=zh e5500RM, e5500 Core Reference Manual with Updates - Reference Manual /secured/assets/documents/en/reference-manual/e5500RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 4 Y N e5500RM, e5500 Core Reference Manual with Updates - Reference Manual 3.7 MB E5500RM N 1320675592951722488289 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 2016-10-31 1319210247754725815434 PSP 8 Jun 26, 2014 Reference Manual This reference manual describes the resources defined for the Power ISA embedded environment. Registration without Disclaimer /secured/assets/documents/en/reference-manual/EREF_RM.pdf English documents 10448185 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EREF_RM&lang_cd=zh EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /secured/assets/documents/en/reference-manual/EREF_RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 10.4 MB EREF_RM N 1319210247754725815434 /secured/assets/documents/en/reference-manual/DPAARM.pdf 2016-10-31 1301610099994679235703 PSP 9 Nov 4, 2011 Reference Manual This manual describes the core set of DPAA functionality implemented in many QorIQ<sup>&#174;</sup> chips, and identifies those portions of the DPAA whose implementation varies from chip to chip. Registration without Disclaimer /secured/assets/documents/en/reference-manual/DPAARM.pdf English documents 19426366 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=DPAARM&lang_cd=zh QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual /secured/assets/documents/en/reference-manual/DPAARM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 2 Y N QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual 19.4 MB DPAARM N 1301610099994679235703 /secured/assets/documents/en/reference-manual/P5020SECRM.pdf 2011-10-28 1319838154290711097752 PSP 10 Oct 28, 2011 Reference Manual Registration without Disclaimer /secured/assets/documents/en/reference-manual/P5020SECRM.pdf English documents 4696534 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=P5020SECRM&lang_cd=zh P5020 Security (SEC 4.2) Reference Manual /secured/assets/documents/en/reference-manual/P5020SECRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N P5020 Security (SEC 4.2) Reference Manual 4.7 MB P5020SECRM N 1319838154290711097752 应用笔记 19 /docs/en/application-note/AN5295.pdf 2016-10-31 1464124094029726989039 PSP 11 May 24, 2016 Application Note AN5295: This application note outlines some common bring-up issues that customers may face when using the Serial RapidIO (SRIO) protocol on NXP QorIQ<sup>&#174;</sup> devices. The document covers issues related to device errata, hardware design, and software or configuration that may affect SRIO operation or performance. These guidelines aim to help with debugging problems and speed up the bring-up process. None /docs/en/application-note/AN5295.pdf English documents 401764 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5295.pdf AN5295, QorIQ Serial RapidIO Debug Tips - Application Note /docs/en/application-note/AN5295.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN5295, QorIQ Serial RapidIO Debug Tips - Application Note 401.8 KB AN5295 N 1464124094029726989039 /docs/zh/application-note/AN5260.pdf 2016-10-31 1456317293250700197105zh PSP 12 Feb 24, 2016 Application Note AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). None /docs/zh/application-note/AN5260.pdf Chinese documents 1027928 None 645036621402383989 2022-12-07 N /docs/zh/application-note/AN5260.pdf PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf documents 645036621402383989 Application Note N zh None Y pdf 0 N N PBL Configuration using QCVS Application Note 1.0 MB AN5260 N 1456317293250700197105 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 13 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /docs/en/application-note/AN4039.pdf 2016-10-31 1264810112254717714233 PSP 14 Nov 11, 2014 Application Note AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. None /docs/en/application-note/AN4039.pdf English documents 468655 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4039.pdf AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf documents 645036621402383989 Application Note N en None pdf 4 N N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 468.7 KB AN4039 N 1264810112254717714233 /secured/assets/documents/en/application-note/AN4848.pdf 2016-10-31 1390372586014711432307 PSP 15 Jan 21, 2014 Application Note AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4848.pdf English documents 1207848 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4848&lang_cd=zh AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /secured/assets/documents/en/application-note/AN4848.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 1.2 MB AN4848 N 1390372586014711432307 /docs/en/application-note/AN4531.pdf 2016-10-31 1363012931515701443659 PSP 16 Dec 16, 2013 Application Note This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. None /docs/en/application-note/AN4531.pdf English documents 269380 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4531.pdf AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf documents 645036621402383989 Application Note N en None pdf 2 N N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 269.4 KB AN4531 N 1363012931515701443659 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 17 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940&lang_cd=zh AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /docs/en/application-note/AN4375.pdf 2016-10-31 1329517560294722281831 PSP 18 Jun 21, 2012 Application Note This document describes how to calculate the maximum frequency and transfer formats and includes eSPI programming examples. None /docs/en/application-note/AN4375.pdf English documents 216552 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4375.pdf QorIQ eSPI Controller Register Setting Considerations and Programming Examples /docs/en/application-note/AN4375.pdf documents 645036621402383989 Application Note N en None pdf 1 N N QorIQ eSPI Controller Register Setting Considerations and Programming Examples 216.6 KB AN4375 N 1329517560294722281831 /docs/en/application-note/AN4326.pdf 2016-10-31 1309961595210675753552 PSP 19 Jul 6, 2011 Application Note This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. None /docs/en/application-note/AN4326.pdf English documents 743199 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4326.pdf Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf documents 645036621402383989 Application Note N en None pdf 0 N Verification of the IEEE 1588 Interface 743.2 KB AN4326 N 1309961595210675753552 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 20 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311&lang_cd=zh SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN4290.pdf 2016-10-31 1301697264409722558859 PSP 21 Apr 1, 2011 Application Note This document describes how to initialize and configure some of the individual elements of the DPAA to send packets in and out of the device. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4290.pdf English documents 648695 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4290&lang_cd=zh Configuring the Data Path Acceleration Architecture (DPAA) /secured/assets/documents/en/application-note/AN4290.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Configuring the Data Path Acceleration Architecture (DPAA) 648.7 KB AN4290 N 1301697264409722558859 /docs/en/application-note/AN3423.pdf 2016-10-31 1287581868481730872047 PSP 22 Oct 6, 2010 Application Note None /docs/en/application-note/AN3423.pdf English documents 141965 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3423.pdf Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors /docs/en/application-note/AN3423.pdf documents 645036621402383989 Application Note N en None pdf 0 N Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors 142.0 KB AN3423 N 1287581868481730872047 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 23 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939&lang_cd=zh DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN4064.pdf 2016-10-31 1269842191514722596708 PSP 24 Mar 28, 2010 Application Note AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. None /docs/en/application-note/AN4064.pdf English documents 576818 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4064.pdf AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 576.8 KB AN4064 N 1269842191514722596708 /docs/en/application-note/AN4056.pdf 2016-10-31 1264143083962735811350 PSP 25 Feb 18, 2010 Application Note This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. None /docs/en/application-note/AN4056.pdf English documents 514364 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4056.pdf Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf documents 645036621402383989 Application Note N en None pdf 1 N Understanding SYSCLK Jitter 514.4 KB AN4056 N 1264143083962735811350 /docs/en/application-note/AN3638.pdf 2016-10-31 1213738938672737755656 PSP 26 Oct 26, 2009 Application Note NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. None /docs/en/application-note/AN3638.pdf English documents 495318 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3638.pdf The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf documents 645036621402383989 Application Note N en None pdf 2 N N The SystemID Format for Power Architecture™ Development Systems 495.3 KB AN3638 N 1213738938672737755656 /secured/assets/documents/en/application-note/AN3869.pdf 2016-10-31 1244236817778728476903 PSP 27 Jun 5, 2009 Application Note This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3869.pdf English documents 692438 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3869&lang_cd=zh Implementing SGMII Interfaces on the PowerQUICC™ III /secured/assets/documents/en/application-note/AN3869.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Implementing SGMII Interfaces on the PowerQUICC™ III 692.4 KB AN3869 N 1244236817778728476903 /docs/en/application-note/AN3532.pdf 2016-10-31 1196228463425717224884 PSP 28 Nov 27, 2007 Application Note This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. None /docs/en/application-note/AN3532.pdf English documents 572952 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3532.pdf Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf documents 645036621402383989 Application Note N en None pdf 0 N Error Correction and Error Handling on PowerQUICC (TM) III Processors 573.0 KB AN3532 N 1196228463425717224884 /docs/en/application-note/AN2910.pdf 2016-10-31 1128961595061725581551 PSP 29 Mar 27, 2007 Application Note These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. None /docs/en/application-note/AN2910.pdf English documents 619650 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2910.pdf Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf documents 645036621402383989 Application Note N en None pdf 2 N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 619.7 KB AN2910 N 1128961595061725581551 应用笔记软件 1 /docs/en/application-note-software/AN3372.pdf 2016-10-31 1181767584945705509512 PSP 30 Jun 13, 2007 Application Note Software This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. None /docs/en/application-note-software/AN3372.pdf English documents 163681 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3372.pdf Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf documents 789425793691620447 Application Note Software N en None pdf 0 N Challenges in Testing for Power Rail Shorts with New Technologies 163.7 KB AN3372 N 1181767584945705509512 手册 2 /docs/en/brochure/PWRARBYNDBITSTA.pdf 2016-10-31 1326753923169722820717 PSP 31 Feb 7, 2012 Brochure None /docs/en/brochure/PWRARBYNDBITSTA.pdf English documents 477805 None 712453003803778552 2022-12-07 /docs/en/brochure/PWRARBYNDBITSTA.pdf Trust Architecture: Freescale’s Security Solution for Industrial Control Systems (ICS) /docs/en/brochure/PWRARBYNDBITSTA.pdf documents 712453003803778552 Brochure N en None pdf 0 N Trust Architecture: Freescale’s Security Solution for Industrial Control Systems (ICS) 477.8 KB PWRARBYNDBITSTA N 1326753923169722820717 /docs/en/brochure/P2P3P5APPBRF.pdf 2016-10-31 1316699641906701481590 PSP 2 Sep 14, 2012 Brochure 手册 The new QorIQ<sup>&#174;</sup> P2040/P2041 and P3041 processors expand the reach of NXP&#8217;s P4 platform into lower power applications. The P2040/P2041 and P3041 processors integrate four e500mc cores based on Power Architecture technology running up to 1.5 GHz within 12 watts. The new P5020 and P5010 processors offer NXP&#8217;s highest single-threaded performance for next-generation embedded control plane applications. With frequencies scaling to 2.2 GHz. None /docs/en/brochure/P2P3P5APPBRF.pdf English 758908 None Brochure 2022-12-07 N /docs/en/brochure/P2P3P5APPBRF.pdf QorIQ P2040/P2041, P3 and P5 Series - Brochures /docs/en/brochure/P2P3P5APPBRF.pdf documents 712453003803778552 Brochure N Y en None t518 pdf 1 N N QorIQ P2040/P2041, P3 and P5 Series - Brochures 758.9 KB P2P3P5APPBRF N 1316699641906701481590 支持信息 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 33 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/P5020_P5010PECI.pdf 2016-10-31 1292347733521725919077 PSP 34 Dec 10, 2010 Supporting Information None /docs/en/supporting-information/P5020_P5010PECI.pdf English documents 22834 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/P5020_P5010PECI.pdf P5020_P5010 Family Customer Export Control Information /docs/en/supporting-information/P5020_P5010PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 0 N N P5020_P5010 Family Customer Export Control Information 22.8 KB P5020_P5010PECI N 1292347733521725919077 数据手册 1 /secured/assets/documents/en/data-sheet/P5020EC.pdf 2013-03-19 1363723529239706397087 PSP 5 Mar 2, 2015 Data Sheet The P5020 and P5010 QorIQ<sup>&#174;</sup> integrated communication processor combines Power Architecture&#174; processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications. Registration without Disclaimer /secured/assets/documents/en/data-sheet/P5020EC.pdf English documents 3078934 None 980000996212993340 2023-06-18 Y /webapp/Download?colCode=P5020EC&lang_cd=zh P5020/P5010 QorIQ<sup>&#174;</sup> Integrated Processor Hardware Specifications - Data Sheet /secured/assets/documents/en/data-sheet/P5020EC.pdf documents 980000996212993340 Data Sheet N en Extended Y pdf 1 Y N P5020/P5010 QorIQ<sup>&#174;</sup> Integrated Processor Hardware Specifications - Data Sheet 3.1 MB P5020EC N 1363723529239706397087 白皮书 6 /docs/en/white-paper/QORIQPMWP.pdf 2017-03-30 1419964678458711207150 PSP 35 Mar 30, 2017 White Paper QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. None /docs/en/white-paper/QORIQPMWP.pdf English documents 1418055 None 918633085541740938 2023-06-19 N /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf documents 918633085541740938 White Paper N en None pdf 0 N N QORIQPMWP, QorIQ Power Management - White Paper 1.4 MB QORIQPMWP N 1419964678458711207150 /docs/en/white-paper/QORIQDPAAWP.pdf 2016-10-31 1338565191762730130183 PSP 36 Jun 1, 2012 White Paper This white paper demonstrates how to best architect software to leverage the DPAA hardware. None /docs/en/white-paper/QORIQDPAAWP.pdf English documents 1051628 None 918633085541740938 2022-12-07 N /docs/en/white-paper/QORIQDPAAWP.pdf QorIQ DPAA Primer for Software Architecture /docs/en/white-paper/QORIQDPAAWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N QorIQ DPAA Primer for Software Architecture 1.1 MB QORIQDPAAWP N 1338565191762730130183 /secured/assets/documents/en/white-paper/QORIQTAWP.pdf 2016-10-31 1283981132878727112937 PSP 37 May 10, 2011 White Paper This paper discusses the objectives of the trust architecture, how it works, and logistical considerations. Registration without Disclaimer /secured/assets/documents/en/white-paper/QORIQTAWP.pdf English documents 650609 None 918633085541740938 2022-12-07 Y /webapp/Download?colCode=QORIQTAWP&lang_cd=zh An Introduction to the QorIQ Platform's Trust Architecture /secured/assets/documents/en/white-paper/QORIQTAWP.pdf documents 918633085541740938 White Paper N en Extended Y pdf 2 Y N An Introduction to the QorIQ Platform's Trust Architecture 650.6 KB QORIQTAWP N 1283981132878727112937 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf 2016-10-31 1289917463417712987902 PSP 38 Nov 16, 2010 White Paper CritialBlue&#13;&#10;&#13;&#10;Prism software None /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf English documents 673125 None 918633085541740938 2022-12-07 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf Tuning QorIQ Processor Performance /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf documents 918633085541740938 White Paper N en None pdf 0 N Tuning QorIQ Processor Performance 673.1 KB LTEWHTPPRCRTBLA4 N 1289917463417712987902 /docs/en/white-paper/64BTTCHNLGYWP.pdf 2010-06-22 1276778683844715153792 PSP 39 Jun 16, 2010 White Paper The new NXP e5500 core is the latest technology evolution in the QorIQ<sup>&#174;</sup> family of communications platforms, enabling applications to take advantage of 64 bits of data per clock cycle. None /docs/en/white-paper/64BTTCHNLGYWP.pdf English documents 227035 None 918633085541740938 2022-12-07 /docs/en/white-paper/64BTTCHNLGYWP.pdf Introducing the e5500 Core /docs/en/white-paper/64BTTCHNLGYWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N Introducing the e5500 Core 227.0 KB 64BTTCHNLGYWP N 1276778683844715153792 /docs/en/white-paper/QORIQSECBOOTWP.pdf 2016-10-31 1317136062337713598350 PSP 3 Jan 25, 2013 White Paper 白皮书 Security continues to be an increasingly important concern in the design of modern systems. Threats against networks and network-connected&#13;&#10;devices are real and growing. With an estimated $40 billion (USD)* of data loss per year, service providers and end-users are becoming painfully&#13;&#10;aware of the consequences of unsecured networks and databases. None /docs/en/white-paper/QORIQSECBOOTWP.pdf English 494394 None White Paper 2023-06-19 N /docs/en/white-paper/QORIQSECBOOTWP.pdf Secure Boot - White Paper /docs/en/white-paper/QORIQSECBOOTWP.pdf documents 918633085541740938 White Paper N Y en None t530 pdf 1 N N Secure Boot - White Paper 494.4 KB QORIQSECBOOTWP N 1317136062337713598350 简介 2 /docs/en/fact-sheet/P5020DSFS.pdf 2016-10-31 1316723002854716246902 PSP 1 Mar 11, 2013 Fact Sheet 简介 The QorIQ<sup>&#174;</sup> P5020DS is a flexible development system based on the dual-core 32/64-bit moded P5020 device. The board, with its 2.0 GHz P5020 and rich I/O mix, is intended for evaluation of the QorIQ P5020/P5010 processor in networking, telecom and industrial applications, where its highperformance, high-efficiency core and integration make it very well suited as a control plane processor. None /docs/en/fact-sheet/P5020DSFS.pdf English 243469 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/P5020DSFS.pdf QorIQ P5020 Development System Fact Sheet /docs/en/fact-sheet/P5020DSFS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 1 N N QorIQ P5020 Development System Fact Sheet 243.5 KB P5020DSFS N 1316723002854716246902 /docs/en/fact-sheet/QP5020FS.pdf 2010-06-14 1275057777362722058756 PSP 4 Apr 23, 2014 Fact Sheet 简介 The QorIQ<sup>&#174;</sup> P5 family delivers scalable 64-bit processing with single-, dual- and quad-core devices. With frequencies scaling up to 2.0 GHz, a tightly coupled cache hierarchy for low latency and integrated hardware acceleration, the P5020 (dual-core) and P5010 (single-core) devices are ideally suited for compute intensive, power-conscious control plane applications. None /docs/en/fact-sheet/QP5020FS.pdf English 130794 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/QP5020FS.pdf QorIQ<sup>&#174;</sup> P5020/P5010 Communications Processors - Fact Sheet /docs/en/fact-sheet/QP5020FS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 6 N N QorIQ<sup>&#174;</sup> P5020/P5010 Communications Processors - Fact Sheet 130.8 KB QP5020FS N 1275057777362722058756 true Y Products

文档

快速参考恩智浦 文档类别.

筛选条件

1-10 / 39 文件

紧凑列表

产品简介 (1)
参考手册 (5)
应用笔记 (19)
展开

设计文件

软件

快速参考恩智浦 软件类型.

筛选条件

4 软件文件

注意: 推荐在电脑端下载软件，体验更佳。

培训

筛选条件

支持

您需要什么帮助?

  • Narrow your search
搜索

近期查看的产品

There are no recently viewed products to display.

查看或编辑浏览历史