设计文件
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9-bit to 18-bit HSTL-to-LVTTL memory address latch
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The HSTL16918 is a 9-bit to 18-bit D-type latch designed for 3.15 to 3.45 V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels.
The HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE) input.
Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE is LOW the Q outputs of the corresponding nine latches follow the D inputs. When LE is taken HIGH, the Q outputs are latched at the levels set up at the D inputs.
The HSTL16918 is characterized for operation from 0 to +70 Cel.
购买/参数
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