Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
封装
CQFP184: CQFP184, ceramic, quad flat package; 184 terminals; 0.65 mm pitch; 31 mm x 31 mm x 3.5 mm body
购买选项
MC68040FE40A
使用寿命终止
12NC: 935325175157
详细信息
订购
工作特点
| 参数 | 值 |
|---|---|
Security Status | COMPANY PUBLIC |
Description | 32BIT W/ CACHE, MMU, FPU |
| 参数 | 值 |
|---|---|
Number of pins | 184 |
Package Style | CQFP |
环境
| 部件/12NC | 无铅 | 欧盟 RoHS | 无卤素 | RHF指标 | 二级互连 | REACH SVHC | 重量（mg） |
|---|---|---|---|---|---|---|---|
MC68040FE40A(935325175157) | No | Yes Certificate Of Analysis (CoA) | Yes |  | e3 | REACH SVHC | 10566.95 |
质量
| 部件/12NC | 安全保障功能安全 | 湿度灵敏度等级(MSL) | 封装体峰值温度（PPT）（C°） | Maximum Time at Peak Temperatures (s) | |||
|---|---|---|---|---|---|---|---|
| 铅焊接 | 铅焊接 | 无铅焊接 | 铅焊接 | 无铅焊接 | |||
MC68040FE40A (935325175157) | No | 1 | 260 | 260 | 40 | 40 | |
配送
| 部件/12NC | 协调关税 (美国)免责声明 | 出口控制分类编号 (美国) |
|---|---|---|
MC68040FE40A (935325175157) | 854231 | 3A991A2 |
停产和更换部件数据
| 部件/12NC | 停产通知 | 上次购买日期 | 上次发货日期 |
|---|---|---|---|
MC68040FE40A (935325175157) | - | 2014-11-21 | 2015-11-21 |
更多信息 MC68040
Archived content is no longer updated and is made available for historical reference only.
The MC68040, MC68040V, MC68LC040, and MC68EC040 are NXP® Semiconductors (formerly Motorola, Inc., Semiconductor Products Sector) fourth generation of M68000-compatible, high-performance, 32-bit microprocessors. All four devices are virtual memory microprocessors employing multiple concurrent execution units and a highly integrated architecture that provides very high performance. They integrate an MC68030-compatible integer unit (IU) and two independent caches. The MC68040, MC68040V, and MC68LC040 contain dual, independent, demand-paged memory management units (MMUs) for instruction and data stream accesses and independent, 4-Kbyte instruction and data caches. The MC68040 contains an MC68881/MC68882-compatible floating-point unit (FPU). The use of multiple independent execution pipelines, multiple internal buses, and a full internal Harvard architecture, including separate physical caches for both instruction and data accesses, achieves a high degree of instruction execution parallelism on all three processors. The on-chip bus snoop logic, which directly supports cache coherency in multileader applications, enhances cache functionality.