Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
封装
LQFP144: LQFP144, plastic, low profile quad flat package; 144 terminals; 0.5 mm pitch; 20 mm x 20 mm x 1.4 mm body
购买选项
DSP56303AG100
使用寿命终止
12NC: 935320944557
详细信息
订购
DSP56303AG100R2
使用寿命终止
12NC: 935320944528
详细信息
订购
工作特点
| 参数 | 值 |
|---|---|
Security Status | COMPANY PUBLIC |
Description | 24-BIT DSP PB-FREE |
| 参数 | 值 |
|---|---|
Number of pins | 144 |
Package Style | LQFP |
环境
| 部件/12NC | 无铅 | 欧盟 RoHS | 无卤素 | RHF指标 | 二级互连 | REACH SVHC | 重量（mg） |
|---|---|---|---|---|---|---|---|
DSP56303AG100(935320944557) | Yes | Yes Certificate Of Analysis (CoA) | No |  | e3 | REACH SVHC | 1319.1 |
DSP56303AG100R2(935320944528) | Yes | Yes Certificate Of Analysis (CoA) | No | | e3 | REACH SVHC | 1319.1 |
质量
| 部件/12NC | 安全保障功能安全 | 湿度灵敏度等级(MSL) | 封装体峰值温度（PPT）（C°） | Maximum Time at Peak Temperatures (s) | |||
|---|---|---|---|---|---|---|---|
| 无铅焊接 | 无铅焊接 | 无铅焊接 | |||||
DSP56303AG100 (935320944557) | No | 3 | 260 | 40 | |||
DSP56303AG100R2 (935320944528) | No | 3 | 260 | 40 | |||
配送
| 部件/12NC | 协调关税 (美国)免责声明 | 出口控制分类编号 (美国) |
|---|---|---|
DSP56303AG100 (935320944557) | 854231 | 3A991A2 |
DSP56303AG100R2 (935320944528) | 854231 | 3A991A2 |
停产和更换部件数据
产品变更通知
| 部件/12NC | 发行日期 | 生效日期 | 产品更改通知 | 标题 |
|---|---|---|---|---|
DSP56303AG100 (935320944557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
DSP56303AG100R2 (935320944528) | ||||
DSP56303AG100 (935320944557) | 2019-09-25 | 2019-09-26 | 201909022DN | Discontinuance Notice for DSP56303 68360 PBGA only 8569 P5020 8272 Family Lead only 8313 Family Lead only |
DSP56303AG100R2 (935320944528) |
更多信息 DSP56303
The DSP56303 is intended for use in telecommunication applications, such as multi-line voice/data/fax processing, videoconferencing, audio applications, control, and general digital signal processing.
The DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high performance, single clock cycle per instruction engine providing a twofold performance increase over Our popular DSP56000 core family, while retaining code compatibility. Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0-3.6 volts. The DSP56300 core family offers a new level of performance in speed and power provided by its rich instruction set and low power dissipation, enabling a new generation of wireless, telecommunications, and multimedia products.
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