1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications | NXP 半导体

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1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

SSTUA32866EC
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The SSTUA32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM.

The SSTUA32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.

The SSTUA32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm x 5.5 mm).

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SSTUA32866EC
数据手册

替换部件: SSTUB32866EC

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N true 0 PSPSSTUA32866ECzh 2 封装信息 Package Information t790 1 数据手册 Data Sheet t520 1 zh zh zh 数据手册 Data Sheet 1 1 2.0 English 1442061378966719167458 PSP 153.0 KB None None documents None 1442061378966719167458 /docs/en/data-sheet/SSTUA32866.pdf 153000 /docs/en/data-sheet/SSTUA32866.pdf SSTUA32866 documents N 2015-09-12 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications /docs/en/data-sheet/SSTUA32866.pdf /docs/en/data-sheet/SSTUA32866.pdf Data Sheet N 980000996212993340 2022-12-07 pdf en Mar 26, 2007 980000996212993340 Data Sheet Y N 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications 封装信息 Package Information 1 2 1.0 English 1455079233858703238410 PSP 438.0 KB None None documents None 1455079233858703238410 /docs/en/package-information/SOT536-1.pdf 438000 /docs/en/package-information/SOT536-1.pdf SOT536-1 documents N 2016-02-09 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm /docs/en/package-information/SOT536-1.pdf /docs/en/package-information/SOT536-1.pdf Package Information N 302435339416912908 2022-12-07 pdf en Feb 8, 2016 302435339416912908 Package Information Y N plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm false 0 SSTUA32866EC downloads zh-Hans true 1 Y PSP 封装信息 1 /docs/en/package-information/SOT536-1.pdf 2016-02-09 1455079233858703238410 PSP 2 Feb 8, 2016 Package Information None /docs/en/package-information/SOT536-1.pdf English documents 438000 None 302435339416912908 2022-12-07 /docs/en/package-information/SOT536-1.pdf plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm /docs/en/package-information/SOT536-1.pdf documents 302435339416912908 Package Information N en None Y pdf 1.0 N plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm 438.0 KB SOT536-1 N 1455079233858703238410 数据手册 1 /docs/en/data-sheet/SSTUA32866.pdf 2015-09-12 1442061378966719167458 PSP 1 Mar 26, 2007 Data Sheet None /docs/en/data-sheet/SSTUA32866.pdf English documents 153000 None 980000996212993340 2022-12-07 /docs/en/data-sheet/SSTUA32866.pdf 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications /docs/en/data-sheet/SSTUA32866.pdf documents 980000996212993340 Data Sheet N en None Y pdf 2.0 N 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications 153.0 KB SSTUA32866 N 1442061378966719167458 true Y Products

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