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Fast dual bidirectional bus buffer[PCA9521]
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The PCA9521 is a monolithic bipolar integrated circuit for bus buffering in applications including I²C-bus, SMBus, PMBus, and other systems based on similar principles.
The buffer extends the bus load limit by buffering both the SCL and SDA lines. It supports up to 400 pF loads on each side of the buffer at 400 kHz. Higher capacitance is supported at lower speeds, and lower capacitance at higher speeds up to 1 MHz.
The enable function allows sections of the bus to be isolated. Individual parts of the system can be brought on-line successively. This means a controlled start-up using a diverse range of components, operating speeds and loads is easily achieved. Systems employing removable components on a back-plane (for example, telecommunications racks) can use the enable pin and the high-impedance ports on power-down to safely install and remove components in active systems.
Bus level translation between a very wide range of bus voltages, from 1.8 V to 10 V, is supported. This feature provides enormous flexibility in interfacing systems of different technologies.
The operation of the PCA9521 provides one of the fastest response times of such bidirectional buffers, ensuring any glitches (common to other buffers) are kept well within the 50 ns I²C-bus specification. Additionally, it does this without the need for ‘rise-time accelerators’ which, combined with low noise margins, may cause glitches outside of the I²C-bus specification.
PCA9521快速参考恩智浦 文档类别.
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