Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
购买选项
UDA1355H/N2,518
停产
12NC: 935271552518
详细信息
订购
UDA1355H/N2,551
停产
12NC: 935271552551
详细信息
订购
UDA1355H/N2,557
停产
12NC: 935271552557
详细信息
订购
工作特点
| 参数 | 值 |
|---|---|
Product description | Stereo audio ADC, stereo audio DAC, with SPDIF interface |
Input formats | Analog, I2S, SPDIF |
Output formats | Analog, I2S, SPDIF |
Control Interface | I2C, L3, Static |
T[min] - [max] | -40 - +85 |
Resolution [max] | 24 |
| 参数 | 值 |
|---|---|
Sampling rate [min] - [max] | 16 - 100 |
Power dissipation [Typ] | 103 |
ADC SNo [Typ] | 97 |
DAC SNo [Typ] (dB) | 98 |
Remarks | Many different usage modes |
环境
| 部件/12NC | 无铅 | 欧盟 RoHS | 无卤素 | RHF指标 | REACH SVHC | 重量（mg） |
|---|---|---|---|---|---|---|
UDA1355H/N2,518(935271552518) | Yes | Yes | Yes |  | REACH SVHC | 425.0 |
UDA1355H/N2,551(935271552551) | Yes | Yes | Yes | | REACH SVHC | 425.0 |
UDA1355H/N2,557(935271552557) | Yes | Yes | Yes | | REACH SVHC | 425.0 |
质量
| 部件/12NC | 安全保障功能安全 | 湿度灵敏度等级(MSL) | 封装体峰值温度（PPT）（C°） | ||
|---|---|---|---|---|---|
| 铅焊接 | 无铅焊接 | 铅焊接 | 无铅焊接 | ||
UDA1355H/N2,518 (935271552518) | - | 2 | 3 | 240 | 260 |
UDA1355H/N2,551 (935271552551) | - | 2 | 3 | 240 | 260 |
UDA1355H/N2,557 (935271552557) | - | 2 | 3 | 240 | 260 |
配送
| 部件/12NC | 协调关税 (美国)免责声明 |
|---|---|
UDA1355H/N2,518 (935271552518) | 854239 |
UDA1355H/N2,551 (935271552551) | 854239 |
UDA1355H/N2,557 (935271552557) | 854239 |
停产和更换部件数据
| 部件/12NC | 停产通知 | 上次购买日期 | 上次发货日期 | 替代器件 |
|---|---|---|---|---|
UDA1355H/N2,518 (935271552518) | - | 2013-12-31 | 2014-06-30 | None |
UDA1355H/N2,551 (935271552551) | - | 2013-12-31 | 2014-06-30 | None |
UDA1355H/N2,557 (935271552557) | - | 2013-12-31 | 2014-06-30 | None |
更多信息 UDA1355H
Archived content is no longer updated and is made available for historical reference only.
The UDA1355H is a single-chip IEC 60958 decoder and encoder with integrated stereo digital-to-analog converters and analog-to-digital converters employing bitstream conversion techniques.
The UDA1355H has a selectable one-of-four SPDIF input (accepting level I, II and III timing) and one SPDIF output which can generate level II output signals with CMOS levels. In microcontroller mode the UDA1355H offers a large variety of possibilities for defining signal flows through the IC, offering a flexible analog, digital and SPDIF converter chip with possibilities for off-chip sound processing via the digital input and output interface.
A lock indicator is available on pin LOCK when the IEC 60958 decoder and the clock regeneration mechanism is in lock. By default the DAC output and the digital data interface output are muted when the decoder is not in lock.
The UDA1355H contains two clock systems which can run at independent frequencies, allowing to lock-on to an incoming SPDIF or digital audio signal, and in the mean time generating a stable signal by means of the crystal oscillator for driving, for example, the ADC or SPDIF output signal.
Using the crystal oscillator (which requires a 12.288 MHz crystal) and the on-chip low jitter PLL, all standard audio sampling frequencies (fs= 32, 44.1 and 48 kHz including half and double these frequencies) can be generated.