Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
特点
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
购买选项
SSTUM32868ET,518
停产
12NC: 935282729518
详细信息
订购
SSTUM32868ET/S,518
停产
12NC: 935283146518
详细信息
订购
工作特点
| 参数 | 值 |
|---|---|
Security Status | COMPANY PUBLIC |
Function | Latches/registered drivers |
Description | 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications |
| 参数 | 值 |
|---|---|
Number of pins | 176 |
Package Style | TFBGA |
环境
| 部件/12NC | 无铅 | 欧盟 RoHS | 无卤素 | RHF指标 | REACH SVHC | 重量（mg） |
|---|---|---|---|---|---|---|
SSTUM32868ET,518(935282729518) | Yes | Yes | Yes |  | REACH SVHC | 222.814 |
SSTUM32868ET/S,518(935283146518) | Yes | Yes | Yes | | REACH SVHC | 220.0 |
质量
| 部件/12NC | 安全保障功能安全 | 湿度灵敏度等级(MSL) | 封装体峰值温度（PPT）（C°） | ||
|---|---|---|---|---|---|
| 无铅焊接 | 铅焊接 | 无铅焊接 | |||
SSTUM32868ET,518 (935282729518) | No | 2 | 240 | 260 | |
SSTUM32868ET/S,518 (935283146518) | - | 2 | 240 | 260 | |
配送
| 部件/12NC | 协调关税 (美国)免责声明 |
|---|---|
SSTUM32868ET,518 (935282729518) | 854239 |
SSTUM32868ET/S,518 (935283146518) | 854239 |
停产和更换部件数据
| 部件/12NC | 停产通知 | 上次购买日期 | 上次发货日期 | 替代器件 |
|---|---|---|---|---|
SSTUM32868ET,518 (935282729518) | - | 2013-06-30 | 2013-12-31 | None |
SSTUM32868ET/S,518 (935283146518) | - | 1998-01-30 | 1998-12-31 | SSTUM32868ET,518 (935282729518) |
更多信息 SSTUM32868ET
Archived content is no longer updated and is made available for historical reference only.
The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.
The SSTUM32868 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it is permanently configured for high output drive strength. This allows use in high density designs with heavier than normal net loading conditions. Furthermore, the SSTUM32868 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register. Finally, the SSTUM32868 is optimized for the fastest propagation delay in the SSTU family of registers.
The SSTUM32868 is packaged in a 176-ball, 8 x 22 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum 6 mm x 15 mm of board space) allows for adequate signal routing and escape using conventional card technology.