Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
特点
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
购买选项
P80C552EFB/08,557
停产
12NC: 935237120557
详细信息
订购
工作特点
| 参数 | 值 |
|---|---|
Security Status | COMPANY PUBLIC |
Description | Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM |
Number of pins | 80 |
| 参数 | 值 |
|---|---|
Package Style | QFP |
Product category | 230-OTP/ROM- |
环境
| 部件/12NC | 无铅 | 欧盟 RoHS | 无卤素 | RHF指标 | REACH SVHC | 重量（mg） |
|---|---|---|---|---|---|---|
P80C552EFB/08,557(935237120557) | Yes | Yes Certificate Of Analysis (CoA) | No |  | REACH SVHC | 1688.8700873999999 |
质量
| 部件/12NC | 安全保障功能安全 | 湿度灵敏度等级(MSL) | 封装体峰值温度（PPT）（C°） | 适合 | MTBF | IR | ||
|---|---|---|---|---|---|---|---|---|
| 铅焊接 | 无铅焊接 | 铅焊接 | 无铅焊接 | |||||
P80C552EFB/08,557 (935237120557) | No | 2 | 3 | 225 | 245 | 2.84 | 2.58397932816537E8 | 0.0 |
配送
| 部件/12NC | 协调关税 (美国)免责声明 |
|---|---|
P80C552EFB/08,557 (935237120557) | 854231 |
停产和更换部件数据
| 部件/12NC | 停产通知 | 上次购买日期 | 上次发货日期 |
|---|---|---|---|
P80C552EFB/08,557 (935237120557) | - | 1998-03-31 | 1998-06-30 |
产品变更通知
| 部件/12NC | 发行日期 | 生效日期 | 产品更改通知 | 标题 |
|---|---|---|---|---|
P80C552EFB/08,557 (935237120557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
更多信息 P80C552EFB
The 80C552/83C552 (hereafter generically referred to as 8XC552) Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 8XC552 has the same instruction set as the 80C51.
Three versions of the derivative exist:
- 83C552?8 kbytes mask programmable ROM
- 80C552?ROMless version of the 83C552
- 87C552?8 kbytes EPROM (described in a separate chapter)
The 8XC552 contains a non-volatile 8k ? 8 read-only program memory (83C552), a volatile 256 ? 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I²C-bus), a "watchdog" timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 8XC552 can be expanded using standard TTL compatible memories and logic.
In addition, the 8XC552 has two software selectable modes of power reduction?idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With a 16 MHz (24 MHz) crystal, 58 pct of the instructions are executed in 0.75 us (0.5 us) and 40 pct in 1.5 us (1 us). Multiply and divide instructions require 3 us (2 us).