Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
购买选项
MC912D60ACPVE8
不推荐用于新设计
12NC: 935312315557
详细信息
订购
工作特点
| 参数 | 值 |
|---|---|
Package Style | LQFP |
环境
| 部件/12NC | 无铅 | 欧盟 RoHS | 无卤素 | RHF指标 | 二级互连 | REACH SVHC | 重量（mg） |
|---|---|---|---|---|---|---|---|
MC912D60ACPVE8(935312315557) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | e3 | REACH SVHC | 1278.3 |
质量
| 部件/12NC | 安全保障功能安全 | 湿度灵敏度等级(MSL) | 封装体峰值温度（PPT）（C°） | Maximum Time at Peak Temperatures (s) | |||
|---|---|---|---|---|---|---|---|
| 无铅焊接 | 无铅焊接 | 无铅焊接 | |||||
MC912D60ACPVE8 (935312315557) | No | 3 | 260 | 40 | |||
配送
| 部件/12NC | 协调关税 (美国)免责声明 | 出口控制分类编号 (美国) |
|---|---|---|
MC912D60ACPVE8 (935312315557) | 854231 | EAR99 |
产品变更通知
| 部件/12NC | 发行日期 | 生效日期 | 产品更改通知 | 标题 |
|---|---|---|---|---|
MC912D60ACPVE8 (935312315557) | 2025-04-16 | 2025-05-26 | 202504007I | Freescale Logo to NXP Logo Product Marking Conversion for All Remaining Former Freescale Products |
MC912D60ACPVE8 (935312315557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
更多信息 68HC912D60A
The 68HC912D60A microcontroller unit (MCU) is a 16-bit device available in two package options, 80-pin QFP and 112-pin TQFP. On-chip peripherals include a 16-bit central processing unit (CPU12), 60K bytes of flash EEPROM, 2K bytes of RAM, 1K bytes of EEPROM, two asynchronous serial communication interfaces (SCI), a serial peripheral interface (SPI), an enhanced capture timer (ECT), two (one on 80QFP) 8-channel, 10-bit analog-to-digital converters (ATD), a four-channel pulse-width modulator
(PWM), and a CAN 2.0 A, B software compatible module (MSCAN12). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the lite integration module (LIM). The 68HC912D60A has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit
allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, 16 (2 on 80QFP) I/O port pins are available with Key-Wake-Up capability from STOP or WAIT mode.