Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
特点
32-bit ARM Cortex-M3 flashless MCU with security features; 200 kB SRAM; Ethernet, two HS USB, LCD, EMC
封装
TFBGA180: plastic thin fine-pitch ball grid array package; 180 balls, 0.8 mm pitch, 12 mm x 12 mm x 0.71 mm body
购买选项
LPC18S50FET180E
正常供应
12NC: 935305909551
详细信息
订购
工作特点
| 参数 | 值 |
|---|---|
Operating Frequency [Max] (MHz) | 180 |
GPIO | 118 |
Ethernet | 1 |
USB Controllers | 2 |
USB (speed) | HS (2x) |
USB (type) | host/device |
CAN | 2 |
UART | 4 |
I2C | 2 |
SPI | 3 |
| 参数 | 值 |
|---|---|
ADC (Channels) | 2 |
ADC (bits) | 10 |
ADC sample rate | 400 ksps |
Timers | 10 |
Timer (bits) | 32 |
SCTimer / PWM | 1 |
Temperature range | -40 °C to +85 °C |
Supply Voltage [min] (V) | 2.4 |
Supply Voltage [max] (V) | 3.6 |
Product category | 140-LPC1800- |
环境
| 部件/12NC | 无铅 | 欧盟 RoHS | 无卤素 | RHF指标 | REACH SVHC | 重量（mg） |
|---|---|---|---|---|---|---|
LPC18S50FET180E(935305909551) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | REACH SVHC | 291.04387240999995 |
质量
| 部件/12NC | 安全保障功能安全 | 湿度灵敏度等级(MSL) | 封装体峰值温度（PPT）（C°） | ||
|---|---|---|---|---|---|
| 无铅焊接 | 铅焊接 | 无铅焊接 | |||
LPC18S50FET180E (935305909551) | No | 3 | 240 | 260 | |
配送
| 部件/12NC | 协调关税 (美国)免责声明 | 出口控制分类编号 (美国) |
|---|---|---|
LPC18S50FET180E (935305909551) | 854231 | 5A992 |
产品变更通知
| 部件/12NC | 发行日期 | 生效日期 | 产品更改通知 | 标题 |
|---|---|---|---|---|
LPC18S50FET180E (935305909551) | 2018-03-17 | 2018-06-25 | 201801009F01 | LPC18xx LPC43xx BGA Package Cu Wire Qualification for NXP-ATKH |
更多信息 LPC18S50FET180
The LPC18S50FET180 is a Arm Cortex-M3 based microcontroller with security features for embedded applications. The Arm Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
The LPC18S50FET180 operates at CPU frequencies of up to 180 MHz. The Arm Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The Arm Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The LPC18S50FET180 includes 200 kB of on-chip SRAM, security features with AES engine, a quad SPI Flash Interface (SPIFI), a State Configurable Timer/PWM (SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.