Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Features
Scalable Entry Level 32-bit Microcontroller (MCU) based on ARM Cortex-M0+/M0 Cores
Buy Options
LPC11E36FBD64/501E
Active
12NC: 935299678551
Details
Order
Operating Features
| Parameter | Value |
|---|---|
Core Type | Arm Cortex-M0 |
Operating Frequency [Max] (MHz) | 50 |
Flash (kB) | 96 |
SRAM (kB) | 12 |
EEPROM (kB) | 4 |
Serial Communication | 1 x I²C, 1 x UART, 2 x SPI |
| Parameter | Value |
|---|---|
Timers [Number, bits] | 2 x 16, 2 x 32 |
PWM [Number, bits] | 2 x 16 |
ADC [Number, bits] | 1 x 10 |
GPIO | 54 |
Supply Voltage [Min to Max] (V) | 1.8 to 3.6 |
Ambient Operating Temperature (Min to Max) (℃) | -40 to 85 |
Environmental
| Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|
LPC11E36FBD64/501E(935299678551) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | REACH SVHC | 345.9 |
Quality
| Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | ||
|---|---|---|---|---|---|
| Lead Soldering | Lead Free Soldering | Lead Soldering | Lead Free Soldering | ||
LPC11E36FBD64/501E (935299678551) | No | 2 | 2 | 240 | 260 |
Shipping
| Part/12NC | Harmonized Tariff (US)Disclaimer | Export Control Classification Number (US) |
|---|---|---|
LPC11E36FBD64/501E (935299678551) | 854231 | 3A991A2 |
Product Change Notice
| Part/12NC | Issue Date | Effective Date | PCN | Title |
|---|---|---|---|---|
LPC11E36FBD64/501E (935299678551) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
More about LPC11E00
The LPC11Exx MCU Family is an Arm® Cortex®-M0+ and Cortex-M0 based- low-cost 32-bit MCU family operating at CPU frequencies of up to 50 MHz. The LPC11Exx MCU family is designed for 8/16-bit micro-controller operations, offering performance, low power, simple instruction set reduce code size compared to existing 8/16-bit architectures.