During the external reset sequence, the CRG block latches the values on

CLK_S[1:0]. 

The data sheet specifies that, if the latched values of CLK_S[1:0] =

"11", CLKOUT is disabled and is equal to "0". However, CLKOUT can remain

at "1" while disabled, if the following conditions are all true:

- CLKOUT was not disabled (i.e. was running), or was already disabled

and set to "1" prior to the current external reset.

- An external reset is applied.

- During the external reset sequence, the CLK_S[1:0] inputs are set to

"11" to disable CLKOUT.

- When the CRG latched the CLK_S[1:0] values, CLKOUT was "1".

 

There is no workaround. 

Bits 0, 1, 2, 3, 6, and 7 are described in the MFR4310 Reference Manuals

as "read-only". However, these bits actually behave as "read/write"

bits, and can be modified by writing to them. 

When writing to the PIER1 register, always write zeros to these bit

locations. 

When the FlexRay module receives a non-null frame that overlaps the end

of a slot or segment, it may write an undetermined 16-bit data item to

an unintended address in the Message Buffers and FIFO Frame

Header/Offset/Status/Data area in the FlexRay Memory.



This erroneous write operation may corrupt the Data Field Offset in the

Message Buffer Header Field. The FlexRay module uses this Data Field

Offset to determine the address to store or fetch frame payload data,

which resides in the FlexRay Memory. If the Data Field Offset was

corrupted, payload data is written to and read from an unpredictable

FlexRay Memory location. As a consequence, the content of any location

in the FlexRay Memory can be corrupted when further frames are received,

and incorrect messages can be transmitted in subsequent slots.



Additionally, when the FlexRay module receives a non-null frame that

overlaps the end of slot, it may write to both receive shadow buffers,

even if a message buffer segment is not used for reception.

 

The application should: 

1) locate the Message Buffer Header Fields for all transmit message

buffers located at lower addresses in FlexRay Memory than those of the

receive message buffers, and 

2) reserve 244 bytes of unused FlexRay Memory space after the last

Message Buffer Header Field, and 

3) observe the Boundary Violation flags PSR3[ABVA] and PSR3[ABVB]. In

the event of a boundary violation, the application should stop the

FlexRay module by the protocol command FREEZE, then reconfigure the

message buffer header fields of the receive message buffers and

reconfigure the receive shadow buffers. 



To avoid an undetermined write access to a non-configured receive shadow

buffer, the application should configure the receive shadow buffers for

all used message buffer segments even if a segment is used only for

transmission.

 

When the FlexRay module has received a frame in the static slot n that

overlaps the end of slot n, then a valid frame received in the following

slot n+1 may be stored incorrectly. In this case, the content of the

Frame Header in the Message Buffer Header Field and Frame Data in the

Message Buffer Data Field of the message buffer subscribed to slot n+1

may be incorrect.



If a receive message buffer is subscribed to slot n+1, the valid frame

bits VFB/VFA in the Slot Status Field and the Data Updated bit DUP in

the Message Buffer Configuration, Control, Status Registers (MBCCSRn)

is set.



If the receive FIFO is subscribed to slot n+1, the Receive FIFO Not

Empty interrupt flag FNEAIF/FNEBIF in the Global Interrupt Flag and

Enable Register is set, and an additional message is put in the receive

FIFO.

 

The FlexRay module sets the boundary violation bit BVB/BVA in the

Slot Status Field of the message buffer subscribed to slot n+1, because

a frame reception is still running at the start of slot n+1. The BVB/BVA

flags can be used to detect the error condition. 



The application should not process received frames with the boundary

violation bit BVA/BVB set in the Slot Status Field of the message buffer.