When using the breakpoint in full mode, there is a chance of a false

match. Internally there 

is a separate read data bus and write data bus. When in full mode 

with the read/write match function is disabled, both buses are always 

compared to the contents of data match register. The circuit should only 

match the active bus on any particular bus cycle. The false match can 

occur if the address matches on a read cycle and matching data is on the 

write data bus or the address matches on a write cycle and the matching 

data is on the read data bus.

 

An SPI configured for slave mode operation can receive incorrect data.

If there are clock edges on SCK while SPE=0, and then SPE is set to one,

the received data will be incorrect. In CPHA=1 mode the SPI will

continue to receive incorrect data as long as SPE=1. 

Depending on the current SPI mode, the following bits must be configured

while disabling the SPI: 



- Set CPHA=1 and ensure that the CPOL-bit is clear every time the SPI is 

  disabled from slave mode. 

- Clear CPHA and ensure that CPOL is clear every time the SPI is

disabled      

  from master mode.



 

The SPIF interrupt flag is erroneously set (and the SPI interrupt vector

is called if the SPIE interrupt enable bit is set) by the following

sequence of events: 



   1. Receive a byte of data with the SPI interface configured in slave 

      mode specifically with the CPHA and the CPOL bits set to 1. 

   2. Clear the SPIF interrupt flag bit in the SPISR status register by 

      reading the SPISR status register followed by a read of SPIDR data 

      register. 

   3. Disable the SPI module by clearing all bits in the SPICR1 control 

      register. 

   4. Re-enable the SPI module with the CPHA and the CPOL bits set to 1. 

   1. Avoid configuring the SPI module with both the CPHA and CPOL bits

      set to 1.

OR

   2. To clear the erroneous SPIF interrupt flag, the following sequence

      must be followed:



   If no other interrupts are configured:



   Wait for a minimum of three bus cycles after re-enabling the SPI

   module, then clear the SPIF interrupt flag by dummy reading the SPISR

   status register followed by the SPIDR data register.



   If other interrupts are configured and enabled:



   1. Disable all interrupts by setting the interrupt mask bit of the

      condition code register (CCR). This can be accomplished by

      executing an SEI instruction.

   2. Re-enable the SPI module by setting the SPE, CPHA and CPOL bits in

      the SPICR1 control register. Wait for a minimum of three bus

      cycles after re-enabling the SPI module, then clear the SPIF

      interrupt flag by dummy reading the SPISR status register followed

      by the SPIDR data register.

   3. Re-enable all interrupts by clearing the interrupt mask bit of the

      CCR. This can be accomplished by executing a CLI instruction.



Notes on using workarounds:



   It is possible that a valid SPI interrupt condition may be masked and

   cleared during the erroneous setting and resetting of the SPIF

   interrupt flag if:



   1. The interrupt service routine of an XIRQ interrupt takes more time

      to execute than the time required to receive a byte of SPI data.

OR

   2. A valid byte of SPI data is received as the SPIF interrupt flag is

      being reset.  

The SPI locks if it is disabled in master mode with CPHA=1 in SPICR1 and

re-enabled in master mode with CPHA=1.

 









 

Make sure that CHPA is not set when SPI is disabled after a

transmission in master mode.



 

In expanded modes with the EMK emulate port k bit set and the EXSTR[1:0]

external access stretch bits 1 & 0 set to 01, 10 or 11 the

non-multiplexed addresses on PK[5:0] change during E clock high phase.



 

If the external access is stretched (EXSTR[1:0] set to 01, 10 or 11) off

chip address latches should be used to register the non-multiplexed

addresses on PK[5:0]. 

The SCI interrupt is only asserted if an odd number of interrupts

are enabled and set. 



For example, if a transmit data register empty and a receive ready

interrupt are active at the same time, the CPU interrupt request 

is not asserted. This can lead to missing interrupts or spurious

interrupts where the request gets deasserted before the CPU fetches the

interrupt vector. These spurious interrupts will be handled by 

direction via the SWI interrupt vector.



 

The problem is minimized by fast interrupt response times and slow

baud rates. Details of a workaround that greatly reduces the possibility

of this erratum occurring during the normal transmission and reception 

of SCI data can be found in Engineering Bulletin EB614 "SCI Interrupt

Errata Workaround for HCS12 Family Devices" at www.nxp.com.



1) Single wire operation - use a mixture of interrupt and polling



Use only the receive interrupt and move the first bytes of a message 

into the transmit queue using transmit data register empty flag 

polling. When a new byte is received and the receive interrupt is 

asserted, the transmit data buffer will be empty and a new byte can be 

written for transmission. 



2) Full duplex operation - use third interrupt method.



If the SCI interrupt is not asserted while a transmit or receive

interrupt is pending (because an even number of interrupts are pending),

the newly received byte will cause an overflow error and generate a

third interrupt. This will assert the CPU interrupt line as an odd

number of interrupts are now active. User software must detect the

overrun error and request a re-transmission of the last message frame.

Use care with this solution as one frame of data is lost and must be

recovered by user software. Flag bits should be polled at a frequency

directly proportional to the baud rate.

 

During reset in emulation expanded modes, Colpitts oscillator may not

selected if PE[7] pin is left floating because the pin is not configured

for pull-up. 

Put an external pull-up on PE[7] pin. 

After the Flash operation mode is changed from Super User Mode to Normal

Mode, the ACCERR flag (FSTAT register) is always set during the

execution of a command sequence. 

Flash operation can be performed in Normal mode by clearing an asserted

ACCERR flag. First intentionally set the flag, and then clear it before

proceeding. 

Protected areas can be programmed and sector-erased in Super User mode -

PVIOL flag does not get set. No misfunctions observed when trying to

mass-erase a protected area. 

No workaround available. 

In super user mode, writes to the FADDR register fail when using

instructions stored on the Flash array. This leads to misfunctions of

Program and Sector-Erase Flash procedures since FADDR value does not

change after a write attempt. 

Workarounds are only available for STORE instructions. 1) Only use STORE

instructions located in even array addresses (See example 1 below). 2)

Use STORE instructions with Indexed Addressing Modes (See example 2

below).



Example 1:

ORG     $8000

MOVB    #$80,CALCFG     ; enter super user mode

LDD     WRITE_ADDRESS

LSRD

ALIGN 1                 ; as12 assembler command

STD     FADDRHI         ; aligement STD command address

UNALIGN 1               ; as12 assembler command

LDD     WRITE_DATA

STD     FDATAHI

...



Example 2:

ORG     $8000

LDX     #FADDRHI        ; set index X register

MOVB    #$80,CALCFG     ; enter super user mode

LDD     WRITE_ADDRESS

LSRD

STD     ,X

LDD     WRITE_DATA

STD     FDATAHI

... 

In a pattern which does the following: 



1. Programs some code into each Flash block (The function of the

programmed code is to try to program a location in the other Flash

block). 



2. Executes this code from each Flash block consecutively. 



Example code: Code in Flash0 to program Flash 1 

START_PROG_CODE_0

NOP ; workaround? **



; if added NOP, programed correct

MOVB #FTS_SUPER,CALCFG ; enter super user mode

LDD #$3000 ; program to block 1 

LSRD

STD FADDRHI

NOP 

LDD #$1234 

STD FDATAHI

MOVB #$20,FCMD 

MOVB #$80,FSTAT

NOP 

NOP 

BRCLR FSTAT,#$40,* 

MOVB #FTS_NORMAL,CALCFG

RTS END_PROG_CODE_0



Code in Flash1 to program Flash 0 

START_PROG_CODE_1 **

NOP ; workaround? **



; if added NOP, programed correct 

MOVB #FTS_SUPER,CALCFG ; enter super user mode

LDD #$D000 ; program to block 0 

LSRD

STD FADDRHI

LDD #$5678 

STD FDATAHI

MOVB #$20,FCMD 

MOVB #$80,FSTAT

NOP 

NOP 

BRCLR FSTAT,#$40,* 

MOVB #FTS_NORMAL,CALCFG

RTS END_PROG_CODE_1



It seems that when the NOP instruction is present, the timing of the STD

FADDRHI instruction is different in the following way: 



1. Without the NOP, the next fetch from the Flash array occurs

immediatelyafter the STD FADDRHI instruction is executed from the core,

hence resulting in the assertion of the array_select signal immediately

after the register_select, and this in turn prevents data being written

into the FADDRHI register. 



2. With the NOP instruction at the beginning, there is an extra cycle

before the array_select is asserted and this gives enough time for the

STD FADDRHI instruction to write the data into the register.

 

In order for this mode to work in the existing implementation, the STD

instruction must be located at an even address in the EXECUTION location

of the code. Adjust with NOP instructions at the beginning of the

routine. 



If the STD FADDRHI executes from an even address, then there is a free

cycle after the write to the register space, and the array select signal

does not assert immediately. But, if the STD is on an odd address, then

there must be a program fetch immediately after the write, and arraysel

asserts. 

If an SPI is enabled in slave mode with the CPHA bit set, all other bits

in their reset state, and SS/SCK pins driven low then clearing the CPHA

bit will cause the SPIF bit to be set three Bus Clock cycles after the

CPHA bit is cleared. 

Change of CPHA bit should only occur while SPI is disabled

(SPE bit cleared). 

The outcome cannot be predicted when accessing even RAM addresses (byte

or word). Accessing odd RAM addresses is unaffected. 

None.

The SPIF interrupt flag is erroneously set and the SPI module locks-up

if the following sequence of events occur:



  1. Receive a byte of data with the SPI interface configured in slave 

     mode. 

  2. Clear the SPIF interrupt flag bit in the SPISR status register by 

     reading the SPISR status register followed by a read of SPIDR data  

     register. 

  3. Disable the SPI module by clearing all bits in the SPICR1 control 

     register except the CPHA (clock phase) bit (set SPICR1 to $04). 

  4. Start the SPI master mode enable sequence by first writing the SPICR1 

     control register to $08 (clearing the CPHA (clock phase) bit and 

     setting the CPOL (clock polarity) bit). At this point the SPIF 

     interrupt flag is erroneously set and the SPI module locks-up. 

Write the SPICR1 control register to $0C (CPHA (clock phase) and CPOL

(clock polarity) bits set) before writing the register to $08 during the

re-enable sequence.

 

The reset conditions of the ECLK control logic in the MEBI 

inhibit the generation of 1 ECLK pulse during the reset 

vector fetch. This can prevent the external logic from 

latching the reset vector address. 

None.

Data can be placed into the SPI Data Register (SPIDR) even though the

SPTEF flag is cleared. The SPTEF flag indicates whether the transmit

buffer is empty (SPTEF=1) or full (SPTEF=0). Data can be placed into the

SPI Data Register by reading SPISR with SPTEF=1 followed by a write to

the SPI Data Register. If SPTEF=0, a write to the SPI Data Register

should be ignored, according to the SPI specification. This is not true

for the current implementation, where data can be placed into the SPI

Data Register though SPTEF=0.





 

Do not write to the SPI Data Register until you have

read SPISR with SPTEF=1. 

When using one or more of channels 0-3 as output compare, while using

the remaining channels 0-3 in the enhanced input capture mode

(TFMOD=1,BUFEN = 1, LATQ = 0 in ICSYS register), the output compare(s)

will take place, but the output compare flag(s) will not be set.



 

If a customer wants to use less than the maximum of 4 Input capture

channels in this mode the other channels left in 0-3 can not be

used as output compares since the OCIF flag never gets set.





 

In normal single chip mode, when security is enabled, it is not 

possible to launch the Program ($20), Sector-Erase ($40) and Erase-

Verify ($05) commands in the flash. The Mass-Erase 

($41) command can be launched. 

To enable the Program ($20), Sector-Erase ($40) 

and Erase-Verify ($05) commands in the flash, security must be 

disabled via the backdoor key sequence. See Flash User Guide for 

details of the backdoor key operation. 

When the SPI is enabled in master mode, with CPHA bit set, back to back

transmissions are possible.



When a transmission completes and a further byte is available in the SPI

Data Register, the second transmission begins direclty after "minimum

trailing time".



The problem occurs, when after the SPTEF flag has been set a further

byte is written into the SPI Data Register during the "1st pulse" of a

subsequent transmission.



                                            |--> next tx 

            7th pulse       8th pulse       1st pulse 

 SCK _______|^^^^^^^|_______|^^^^^^^|_______|^^^^^^^|_______



 SPTEF _____________________________________|^^|____|^^^^^^^^

                                            ^  ^    ^

                                            |  |    |

                                            |  |   SPTEF flag set again

                                            |  |   (WRONG)

                                            |  | 

                                            |  Write to SPIDR during

                                            |  "1st pulse"

                                            |

                                            End of tx SPTEF flag is

                                            set



Then the SPTEF flag is set at the falling SCK edge of the "1st

pulse" and data is transfered from the SPI Data Register to the transmit

shift register. The result is that the transmission is corrupted. 

 

After the SPTEF flag has been set, a delay of 1/2 SCK period has to be

added before storing data into the SPI Data Register.

 

For the flags SCF, ETORF and FIFOR in ATDSTAT0 it is specified that

writing a '1' to the respective flag clears it. This does not work.

Writing '1' to the respective flag has no effect. 



The ETORF flag is also set by a non-active edge, e.g. falling edge

trigger (ETRILE=0, ETRIGP=0). ETORF is set on both falling edges and

rising edges while conversion is in progress. 

SCF 

1. Use the alternative flag clearing mechanisms: 

        a. Write to ATDCTL5 (a new conversion sequence is started) 

        b. If AFFC=1 a result register is read 

ETORF 

1. Use the alternative flag clearing mechanisms: 

        a. Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence

           is aborted) 

        b. Write to ATDCTL5 (a new conversion sequence is started) 

2. Avoid external trigger edges during conversion process by using short

pulses 

3. Ignore ETROF flag 



FIFOR 

1. Use the alternative flag clearing mechanism: 

        a. Start a new conversion sequence

           (write to ATDCTL5 or external trigger)



 

When the SPI is in Mode Fault state (MODF flag set), according to the

specification, all SPI output buffers (SS, SCK, MOSI, MISO) should be

disabled. However, the MISO output buffer is not disabled. 

None.

If a write to ATDCTL5 happens at exactly the bus cycle when an ongoing

conversion sequence ends, the SCF, CCF and (if ASCIE=1)

ASCIF flags remain set and are NOT cleared by a write to ATDCTL5. 

1. Make sure the device is protected from interrupts (temporarily

disable interrupts with the I mask bit).

2. Write to ATDCTL5 twice. 

In SPI slave mode with CPHA set, MISO can change erroneously after a

transmission, two to three bus clock cycles after the sixteenth SCK

edge. This can lead to a hold time violation on the SPI master.

 

There are two possible workarounds for this problem: 



   1. Decrease the bus clock of the slave SPI to satisfy the "Master 

      MISO Hold Time". 

      Tbus(Slave) >= 0.5 * "Master MISO Hold Time"



   2. Software workaround: 

      The slave has to transmit a dummy byte after each data byte, 

      which must fulfil the following requirements: 



      - The first bit of the dummy byte to be transmitted (depending on 

        LSBFE bit) must be equal to the last bit of the data byte 

        transmitted before. The dummy byte has to be stored into SPIDR 

        during the transmission of the corresponding data byte. 

        => MISO does not change after the data byte.

 

      - The Master has to receive two bytes, the data byte and the dummy 

        byte.

        => Master receives the data byte correctly and has to skip the 

           dummy byte. 

According to the observation, input pulse (high/low) whose pulse width

is shorter than delay counter window is mistakenly recognized as as

valid pulse. Hence the ic flags will be set and may result in an IRQ if

IRQ is enabled. 



 

A software workaround is available.



User software should check the logic level of the input capture pin 

within the interrupt service routine and compare this with the logic 

level when the input is not asserted. This can be performed using the 

appropriate registers in the port integration module.



If the pin reads the logic level of the inactive state, the pulse is 

shorter than the time defined in the delay counter control register 

plus the interrupt latency. In this case, the pulse triggering the 

input capture is not valid (too short), hence the interrupt can be 

acknowledged and exited without further action taking place. If the pin 

reads the logic level of the active state, the input pulse is valid and 

the interrupt should be acknowledged and the correct input capture 

service routine executed.



The effectiveness of this workaround must be evaluated by identifying

the worst case latency involved in the call of the ISR. To maximise the

effectiveness of pulse rejection, users must consider checking the 

value in the capture register against the free-running timer on every 

new capture. 

This Erratum applies only to systems where PLL is used to divide down

the osc_clock by a ratio between 2 and 3.



If



1) pll_clock (PLLON=1) is running

and

2) 2 < osc_clock/pll_clock < 3

and

3) full stop mode is entered (STOP instruction with PSTP Bit =0) 



there is a small possibility that when entering full stop mode the chip 

reacts as follows:

1) if self clock mode is disabled (SCME=0)  monitor reset is asserted.

   The system does NOT enter stop mode.

or

2) if self clode mode and SCM interrupt are enabled (SCME=1 and SCMIE=1)

   a self clock mode interrupt is generated. The SCMIF flag is set.

   The system does NOT enter stop mode.

or

3) if  SCME=1 and SCMIE=0 the system will enter full stop mode. 

   But after wakeup self clock mode is entered without doing the 

   specified clock quality check. The SCMIF flag is set. 

1) Avoid osc_clock/pll_clock ratios between 2 and 3.

or

2) if you really require osc_clock/pll_clock ratio between 2 and 3

do the following before going into stop.

a) deselect PLL (PLLSEL=0)

b) turn off PLL (PLLON=0)

c) enter stop

d) exiting stop: turn on PLL again (PLLON=1) 

If the FCLKDIV flash clock divider register has been loaded, and the

flash is not executing a command (flash CCIF command complete flag is

set), the execution of a STOP instruction will erroneously set the

ACCERR access error bit in the FSTAT flash status register. 

The ACCERR bit in the FSTAT register must be cleared after the execution

of a STOP instruction if the FCLKDIV register has been loaded. 

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed

normally programming the array according to the content (word) of the

data register while only the high byte in the FDATA register holds valid

information.  

Avoid the use of MOVB instruction for array program operations.  

The setting of the CCF7-0 flags in ATDSTAT1 register

is not independent of the clearing. 

A clear on CCFx (e.g. Bit AFFC=1 and read of ATDDRx)

which occurs in exactly the same bus cycle as the setting of any other

flag CCFy (x,y = 0,1,..,7; x!=y) masks the setting of CCFy.

CCFy will not set in this special case although the corresponding

conversion has completed and the result (ATDDRy) is valid. 

None.

Starting a new conversion by writing to the ATDCTL5 register should

clear all CCF flags in the ATDSTAT1 register.

This does not always work if the write to ATDCTL5 register

occurs near the end of an ongoing conversion.

Although all CCF flags are cleared one CCF flag might be

set again within the 1st ATD clock period of the new conversion. 

If the unexpected setting of one CCF flag can not be

accepted by the application one of the following

workarounds can be taken:

1) Abort conversion (e.g. by write to ATDCTL3)

   Pause for 2 ATD clock periods

   Start new conversion

2) Ignore first conversion sequence and clear CCF flags

 

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than 

expected. 



 

The specification has been updated. Please refer to revision 01.06 (28

 Apr 2010) or later.



In description of bitfield TCRE in register TSCR2,a note has been added:

TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler

counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to

0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it

will last only one bus cycle then reset to 0.







 

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with

enabled ECLK output to an expanded mode. The ECLK is erroneously held in

the high phase thus the first external bus access does not generate a

rising ECLK edge for the external logic to latch the address. The ECLK

stretches low after the lost access resulting in all following external

accesses to be valid. 

Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access. 

If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM

channel 7 is disabled (PWME7=0) another lower priority function

available on the related pin can take control over the data direction.

This does not lead to a problem if input mode is maintained. If the

alternative function switches to output mode the shutdown function may

unintentionally be triggered by the output data.

 

When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 7 should be selected as an input. 



In the case that this pin is selected as an output or where an

alternative function is enabled which could drive it as an output,

enable PWM channel 7 by setting the PWME7 bit. This prevents an

active shutdown level driven on the (output) pin from resulting in an

emergency shutdown of the enabled PWM channels.

 

Channel 0 – 3 Input Capture interrupts are inhibited when BUFEN=1, 

LATQ=0 and NOVWx=1 if an Input Capture edge occurs during or between a 

read of TCx and TCxH or between a read of TCx/TCxH and clearing of CxF.





Details:



When any of the buffered input capture channels 0 - 3 are configured 

for buffered/queue mode  (BUFEN=1, LATQ=0) each of the channel’s input 

capture holding registers and each channel’s associated pulse 

accumulator and its holding register are enabled. When the input 

capture channel is enabled by writing to a channel’s EDGxB and EDGxA 

bits, both the input capture and input capture holding register are 

considered empty. The first valid edge received after enabling a 

channel will latch the ECT’s free running counter into the input 

capture register (TCx) without setting the channel’s associated CxF 

interrupt flag. The second valid edge received will transfer the value 

of the input capture register, TCx, into the channel’s TCxH holding 

register, latch the current value of the free running timer into the 

input capture register and set the channel’s associated CxF interrupt 

flag. In this condition, both the TCx and TCxH registers are 

considered ‘full’.



If a corresponding channel’s NOVWx bit in the ICOVW register is set, 

the capture register or its holding register cannot be written by a 

valid edge at the input pin unless they are first emptied by reading 

the TCx and TCxH registers. The act of reading the TCx and TCxH 

registers and clearing the channel’s associated CxF interrupt flag 

involves three separate operations. Two 16-bit read operations and an 8-

bit write operation.



If a channel’s associated CxF interrupt flag is cleared before reading 

the TCx and TCxH registers and if a valid input edge occurs during or 

between the reading of the capture and holding register, a channel’s 

associated CxF interrupt flag will no longer be set as the result of 

valid input edges. For example:



Clear CxF

    |

    |

    V

Read TCx <----+

    |         |

    |<--------+--- Valid Input Edge Occurs

    V         |

Read TCxH <---+



If the TCx and TCxH registers are read before a channel’s associated 

CxF interrupt flag is cleared and if a valid input edge occurs between 

the reading of TCx/TCxH and the clearing of a channel’s associated CxF 

interrupt flag, a channel’s associated CxF interrupt flag will no 

longer be set as the result of valid input edges. For example:



Clear CxF

    |

    |

    V

Read TCx 

    |

    |<------------ Valid Input Edge Occurs

    V

Read TCxH





Systems that service the interrupt request and read the TCx and TCxH 

registers before the next valid edge occurs at a channel’s associated 

input pin will avoid the conditions under which the errata will occur.  

A simple workaround exists for this errata:



1. Clear the input capture channel’s associated CxF bit.

2. Disable the input capture function by writing 0:0 to a channel’s 

   EDGxB and EDGxA bits.

3. Read TCx

4. Read TCxH

5. Re-enable the input capture function by writing to a channel’s EDGxB 

   and EDGxA bits.





Code Example:



unsigned char ICSave;

unsigned int TC0Val;

unsigned int TC0HVal;



ICSave = TCTL4 & 0x03;  /* save state of EDG0B and EDG0A */

TFLG1 = 0x01;           /* clear ECT Channel 0 flag */

TCTL4 &= 0xfc;          /* disable Channel 0 input capture function */

TC0Val = TC0;           /* Read value of TC0 */

TC0HVal = TC0H;         /* Read value of TC0H */

TCTL4 |= ICSave;        /* Restore Channel 0 input capture function */ 

In low power modes (stop/p-stop/wait – PSWAI=1) and during PWM PP7

de-assert and when PWM counter reaching 0, the PWM channel outputs

(PP0-PP6) cannot keep the state which is set by PWMLVL bit.  



 

Before entering low power modes, user can disable the related PWM 

channels and set the corresponding general-purpose IO to be the PWM 

LVL value. After a intend period, restart the PWM channels.

 

When the PWM is used in 16-bit (concatenation) channel and the emergency

shutdown feature is being used, after de-asserting PWM channel 7

(note:PWMRSTRT should be set) the PWM channels (PP0-PP6) do not show the

state which is set by PWMLVL bit when the 16-bit counter is non-zero. 

 

If emergency shutdown mode is required:



In 16-bit concatenation mode, user can disable the related PWM 

channels and set the corresponding general-purpose IO to be the PWM 

LVL value. After a intend period, restart the PWM channels.