General purpose input/output functionality will not be available for

pins, PORTQ[3:0], if fault function is enabled on any one of these 4

pins. The fault function for a fault pin is enabled by setting the

corresponding bit in PMF Fault Pin Enable register (PMFFPIN). 

Do not use General purpose I/O functionality when any one of the 4 fault

pins (PORTQ[3:0]) are enabled for fault functionality. 

 

The PMF manual correction method is one of the 2 methods used to correct

distortion during deadtime generation. Deadtime generation is done only

during complementary mode. This method does not work for Generators B &

C, but works for generator A. 

PortQ[4] can be used for testing manual correction control in

complementary mode - both manual and automatic methods.

This pin can also be used as GPIO.

PortQ[4] pin is the current sense pin for generator A.

 

Using deadtime in complementary mode causes glitches in the PMF output

pins, PP[5:0]. At the start of deadtime, prior to the output rising

edges, glitches of 3-4 ns duration are seen at the PMF outputs.



 

There are 3 types of workaround for this issue:

1. A filter can be used at the pins, which blocks the glitches. The use

of a filter also reduces the pulse-widths of the actual PMF outputs.

Hence, do not use a very low duty cycle in this case.



2. The complementary outputs with deadtime insertion can be mimicked by 

using the output control feature of the PMF.  Just set the OUTCTLx bits 

in the PMF Output Control Register (PMFOUTC) for the corresponding 

channels.  Then, write the desired value to the corresponding bits in 

the PMF Output control Bit Register (PMFOUTB).  Included with this 

errata is an example of how to write to the PMFOUTB Register to achieve 

the emulated deadtime effect.



3. Complementary mode can be used without using deadtime.







 

A spurious BDM SYNC pulse could be transmitted if the delay between 

commands is such that the first negative edge of a new command occurs 

exactly 128 cycles after the last negative edge of the previous command. 

Keep the delay between commands greater than 128 cycles. 

  The polarity of Infrared TX and RX data are inverted compared to what

is defined in IrDA spec. A zero is represented by a narrow low

pulse instead of a narrow high pulse.



 

  If same polarity is required as is defined in IrDA specification, an

external inverter is needed for RXD and TXD pin respectively when

Infrared is enabled.





 

A non-zero prescalar value in PRSCx bit positions in the PMFFQCx (x can

be A, B or C) registers, can cause a slightly reduced deadtime value to

be inserted. The deadtime value is one bus cycle less than the correct

value. 

A "00" data value in the PRSCx bit positions in the PMFFQCx (x can be A,

B or C) can be used for correct deadtime insertion. A, B and C pertain

to the three generator pairs. In this case, the PWM clock frequency is

equal to the bus frequency. 

When the SPI is enabled in master mode, with CPHA bit set, back to back

transmissions are possible.



When a transmission completes and a further byte is available in the SPI

Data Register, the second transmission begins direclty after "minimum

trailing time".



The problem occurs, when after the SPTEF flag has been set a further

byte is written into the SPI Data Register during the "1st pulse" of a

subsequent transmission.



                                            |--> next tx 

            7th pulse       8th pulse       1st pulse 

 SCK _______|^^^^^^^|_______|^^^^^^^|_______|^^^^^^^|_______



 SPTEF _____________________________________|^^|____|^^^^^^^^

                                            ^  ^    ^

                                            |  |    |

                                            |  |   SPTEF flag set again

                                            |  |   (WRONG)

                                            |  | 

                                            |  Write to SPIDR during

                                            |  "1st pulse"

                                            |

                                            End of tx SPTEF flag is

                                            set



Then the SPTEF flag is set at the falling SCK edge of the "1st

pulse" and data is transfered from the SPI Data Register to the transmit

shift register. The result is that the transmission is corrupted. 

 

After the SPTEF flag has been set, a delay of 1/2 SCK period has to be

added before storing data into the SPI Data Register.

 

For the flags SCF, ETORF and FIFOR in ATDSTAT0 it is specified that

writing a '1' to the respective flag clears it. This does not work.

Writing '1' to the respective flag has no effect. 



The ETORF flag is also set by a non-active edge, e.g. falling edge

trigger (ETRILE=0, ETRIGP=0). ETORF is set on both falling edges and

rising edges while conversion is in progress. 

SCF 

1. Use the alternative flag clearing mechanisms: 

        a. Write to ATDCTL5 (a new conversion sequence is started) 

        b. If AFFC=1 a result register is read 

ETORF 

1. Use the alternative flag clearing mechanisms: 

        a. Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence

           is aborted) 

        b. Write to ATDCTL5 (a new conversion sequence is started) 

2. Avoid external trigger edges during conversion process by using short

pulses 

3. Ignore ETROF flag 



FIFOR 

1. Use the alternative flag clearing mechanism: 

        a. Start a new conversion sequence

           (write to ATDCTL5 or external trigger) 

When the SPI is in Mode Fault state (MODF flag set), according to the

specification, all SPI output buffers (SS, SCK, MOSI, MISO) should be

disabled. However, the MISO output buffer is not disabled.

 

None.

The BSR instruction is recognized as a change of flow instruction and

thus causes the trace buffer to be loaded with its destination address.

Since the BSR instruction always branches to the relative address

specified in the instruction, the information stored in the trace buffer

at a BSR is not useful. Thus code making regular use of the BSR

instruction will result in considerable redundancy in trace buffer

contents. 

 

The severity of this bug is directly related to the frequency of BSR 

instruction use. Thus to reduce the impact of this bug, use of the BSR

instruction should be avoided wherever possible.



 

Write accesses to the registers can cause erroneous trigger action when 

using full mode (address AND data) triggers.



A AND B Trigger Mode

Writing to the registers using the A AND B trigger mode may not trigger 

the start of FIFO capture even though a valid successful compare should 

have occurred. Rarely, the same bug will cause an erroneous successful 

trigger even though an address and data match has not occurred.



A AND NOT B Trigger Mode

Writing to the registers using the A AND NOT B trigger mode may cause 

an erroneous successful trigger even though an address and data match 

has not occurred. Rarely, the same bug will prevent a trigger from 

being generated, even though a valid successful compare should have 

occurred. Reads of registers and reads and writes to non-register space 

are not affected by this erratum. 

No workaround exists



 

Several cycles are required after enabling a forced trigger before it

takes effect. 



This is expected behavior but not clearly noted in the user guide. Thus

it is classed as customer information (as opposed to errata). 

Take into account that extra cycles are required when using forced

breakpoints. 

When using LOOP1 debug mode with break to BDM, the trace buffer captures

all change of flow instructions, as if operating in normal capture mode.

This bug is restricted to LOOP1 mode with break to BDM activated, break

to SWI mode is unaffected by this erratum. 

 

When using LOOP1 mode use only break to SWI, not break to BDM. This 

will guarantee correct operation.  

In SPI slave mode with CPHA set, MISO can change erroneously after a

transmission, two to three bus clock cycles after the sixteenth SCK

edge. This can lead to a hold time violation on the SPI master.





 

There are two possible workarounds for this problem: 



   1. Decrease the bus clock of the slave SPI to satisfy the "Master 

      MISO Hold Time". 

      Tbus(Slave) >= 0.5 * "Master MISO Hold Time"



   2. Software workaround: 

      The slave has to transmit a dummy byte after each data byte, 

      which must fulfil the following requirements: 



      - The first bit of the dummy byte to be transmitted (depending on 

        LSBFE bit) must be equal to the last bit of the data byte 

        transmitted before. The dummy byte has to be stored into SPIDR 

        during the transmission of the corresponding data byte. 

        => MISO does not change after the data byte.

 

      - The Master has to receive two bytes, the data byte and the dummy 

        byte.

        => Master receives the data byte correctly and has to skip the 

           dummy byte. 

If a write to ATDCTL5 happens at exactly the bus cycle when an ongoing

conversion sequence ends, the SCF, CCF and (if ASCIE=1)

ASCIF flags remain set and are NOT cleared by a write to ATDCTL5. 

1. Make sure the device is protected from interrupts (temporarily

disable interrupts with the I mask bit).

2. Write to ATDCTL5 twice. 

This Erratum applies only to systems where PLL is used to divide down

the osc_clock by a ratio between 2 and 3.



If



1) pll_clock (PLLON=1) is running

and

2) 2 < osc_clock/pll_clock < 3

and

3) full stop mode is entered (STOP instruction with PSTP Bit =0) 



there is a small possibility that when entering full stop mode the chip 

reacts as follows:

1) if self clock mode is disabled (SCME=0)  monitor reset is asserted.

   The system does NOT enter stop mode.

or

2) if self clode mode and SCM interrupt are enabled (SCME=1 and SCMIE=1)

   a self clock mode interrupt is generated. The SCMIF flag is set.

   The system does NOT enter stop mode.

or

3) if  SCME=1 and SCMIE=0 the system will enter full stop mode. 

   But after wakeup self clock mode is entered without doing the 

   specified clock quality check. The SCMIF flag is set. 

1) Avoid osc_clock/pll_clock ratios between 2 and 3.

or

2) if you really require osc_clock/pll_clock ratio between 2 and 3

do the following before going into stop.

a) deselect PLL (PLLSEL=0)

b) turn off PLL (PLLON=0)

c) enter stop

d) exiting stop: turn on PLL again (PLLON=1) 

Starting a command sequence with a MOVB array write instruction (Byte

Write) will not generate an access error. The command is processed

normally programming the array according to the content (word) of the

data register while only the high byte in the FDATA register holds valid

information. 

Avoid the use of MOVB instruction for array program operations. 

If the FCLKDIV flash clock divider register has been loaded, and the

flash is not executing a command (flash CCIF command complete flag is

set), the execution of a STOP instruction will erroneously set the

ACCERR access error bit in the FSTAT flash status register. 

The ACCERR bit in the FSTAT register must be cleared after the execution

of a STOP instruction if the FCLKDIV register has been loaded. 

The flash block protect mechanism allows any FPROT transition in normal

single chip mode. This should not be the case. According to the user

guide FPROT transitions in normal single chip mode should be restricted

to only allow more protection to be added and prohibit transitions to

less protection. 

None.

Flash protection is mirrored once (hence appears twice) in every flash

block. The mirrored protection will occur four pages lower than the

intended protection. For example, if flash page $3F is protected, the

mirrored protection, specified by the FPROT register setting for the

respective block, will occur in flash page $3B. If flash page $3E is

protected, the mirrored protection will occur in page $3A.

 

None.

A write to the flash protection register that is immediately followed by

a flash array write will not set the PVIOL protection violation flag.



Example: 

 MOVB #$FB FPROT     //protect lower portion of flash page $3E 

 STD #$55AA #$8080   //write to protected address (PVIOL flag expected,

but does not occur) 

Perform a legal write of a register immediately after writing to the

FPROT register, before writing to the flash array.



Example: 

MOVB #$FB FPROT    //protect lower portion of flash page $3E 

MOVB #$30 FSTAT    //clear error flags (legal write to register) 

STD #$55AA #$8080  //write to protected address (PVIOL flag sets to show

protection violation) 

The setting of the CCF15-0 flags in ATDSTAT2/1 registers

is not independent of the clearing. 

A clear on CCFx (e.g. Bit AFFC=1 and read of ATDDRx)

which occurs in exactly the same bus cycle as the setting of any other

flag CCFy (x,y = 0,1,..,15; x!=y) masks the setting of CCFy.

CCFy will not set in this special case although the corresponding

conversion has completed and the result (ATDDRy) is valid. 

None.

Starting a new conversion by writing to the ATDCTL5 register should

clear all CCF flags in the ATDSTAT2/1 registers.

This does not always work if the write to ATDCTL5 register

occurs near the end of an ongoing conversion.

Although all CCF flags are cleared one CCF flag might be

set again within the 1st ATD clock period of the new conversion.

 

If the unexpected setting of one CCF flag can not be

accepted by the application one of the following

workarounds can be taken:

1) o Abort conversion (e.g. by write to ATDCTL3)

   o pause for 2 ATD clock periods

   o Start new conversion

2) o ignore first conversion sequence and clear CCF flags 

On the first instance after MCU reset, the SPIDR data register can be

written without reading the SPISR status register with the SPTEF

transmit buffer empty flag set. This is contrary to the specification

which states that writes to the SPIDR are ignored if the SPISR is not

previously read as being set. 

Do not attempt to write the SPIDR data register without first checking

the SPTEF transmit buffer empty flag as set. 

Breakpoints are temporarily disabled while the MCU is executing BDM

firmware code when operating in active BDM mode. It logically follows

that debug module triggers are disabled in the same manner. While tagged

triggers are disabled, forced triggers are not and therefore may cause

the debug module to trigger erroneously.



In most circumstances this will only be a problem in outside range

trigger mode. In order to see an erroneous trigger in another trigger

mode, a forced trigger must be configured in the BDM firmware address

range ($FF00-$FF80) and an exact address bus match must occur. This

memory area would typically contain interrupts, vectors or program code,

and would therefore be a very unlikely location for the configuration of

a forced trigger address.  

Outside range trigger mode should not be used when configuring forced

triggers if the trigger range contains the memory area where the BDM

firmware code resides ($FF00-$FF80) and the user intends to operate the

MCU in active BDM mode.



 

The problem concerns the DBG-CPU interface in DBG mode whilst tagging if

an interrupt occurs at the moment that a tag is attached to an opcode

being loaded into the instruction queue. 



If the DBG module is configured with BDM=DBGBRK=1, BEGIN=0 an event

causing a flag to be set should cause a break to BDM. The symptom is

that the flag gets set but the part does not enter active BDM mode. The

CPU executes the interrupt service routine instead and returns to the

correct position in the program flow but the breakpoint to BDM is

missed. 



The problem does not occur if the DBG module is configured for operation

in BKP mode (BKABEN=1). This is because even if the flag bit is set,

BKABEN bit is not cleared. Thus on returning from the interrupt service

routine the tag is re-applied when the PC is fetched after the interrupt

service routine. Thus the part enters BDM after the interrupt service

routine. 



In BKP mode with TRGSEL=0 no flags are set when a taghit occurs. 

In BKP mode with TRGSEL=1 the flag is also set erroneously, on entering

the interrupt service routine. However the user would typically not

notice the flag being set early unless the service routine were 

exceptionally long, because of the large time needed to read out the

DBGSR (flag bits) over the BKGD pin. In the meantime the part would

typically have entered active BDM anyway when the tag is re-applied.



Furthermore this does not occur on the older BKP module which does not

feature flags to indicate tag hits.  

None.

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command

transmission is detected during this time, the return address will be

manipulated in the BDM shift register. This situation is likely to occur

when a CPU BGND instruction is executed in user code during debugging

under the following conditions:



(i) The BDM module is not enabled AND

(ii) BDM commands are sent from the host



If this situation occurs, the CPU will execute BDM firmware and will

check the status of the ENBDM bit in the BDMSTS register. If the BDM is

disabled, the ENBDM bit will be clear, and hence the BDM firmware will

be exited and the shift register manipulation described above will occur. 

Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared. 

The flash program temperature range specification has been reduced. The

specification now stipulates that flash program operations must take

place between temperatures of 0C and 125C ambient.



In addition, the flash program times have been increased as follows:



                                                   Programming Time 

                                                    Min.      Max.

Single Word Program                      (Tswpgm)    66.0us    99.2us  

Flash Row Program - Consecutive Word     (Tbwpgm)    40.4us    57.8us

Flash Row Program - 64 words             (Tbrpgm)  2608.7us  3742.7us



Actual programming time will vary between the above bounds depending on

flash clock and bus clock frequencies.



Important Notes: 

1) Program time is internally controlled by the flash state machine. 

   No action needs to be taken by users in connection with this erratum.

2) Both flash erase and flash read temperature specifications and 

   operation times are unaffected by this erratum.

3) EEPROM is unaffected by this erratum. 

~



 

None.

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with

enabled ECLK output to an expanded mode. The ECLK is erroneously held in

the high phase thus the first external bus access does not generate a

rising ECLK edge for the external logic to latch the address. The ECLK

stretches low after the lost access resulting in all following external

accesses to be valid. 

Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access. 

When writing or reading the internal BDM resources (address range $FF00

to $FFFF) via BDM hardware commands, the /XCS Chip Select signal is

erroneously driven low during the BDM access. 



The /XCS signal is also driven low for CPU accesses performed to execute

BDM firmware when the CPU is in BDM active mode (BDMACT=1). This

includes the specific read/write cycle of the BDM firmware commands

READ_NEXT and WRITE_NEXT to access the targeted address of BDM firmware.



The R/W signal remains in read state in all these cases. The data

received by the above false external read accesses are discarded by the MCU.

 

None. 

If the PWM emergency shutdown feature is enabled (PWM5ENA=1) and PWM

channel 5 is disabled (PWME5=0) another lower priority function

available on the related pin can take control over the data direction.

This does not lead to a problem if input mode is maintained. If the

alternative function switches to output mode the shutdown function may

unintentionally be triggered by the output data.



 

When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 5 should be selected as an input. 



In the case that this pin is selected as an output or where an

alternative function is enabled which could drive it as an output,

enable PWM channel 5 by setting the PWME5 bit. This prevents an

active shutdown level driven on the (output) pin from resulting in an

emergency shutdown of the enabled PWM channels.



 

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than 

expected. 



 

The specification has been updated. Please refer to revision 01.02 (06 

May 2010) or later.



In description of bitfield TCRE in register TSCR2,a note has been added:

TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler

counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to

0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it

will last only one bus cycle then reset to 0.













 

When the PWM is used in 16-bit (concatenation) channel and the 

emergency

shutdown feature is being used, after de-asserting PWM channel 5

(note:PWMRSTRT should be set) the PWM channels (PP0-PP4) do not show 

the

state which is set by PWMLVL bit when the 16-bit counter is non-zero. 



 

None. 

In low power modes (stop/p-stop/wait ?PSWAI=1) and during PWM PP5

de-assert and when PWM counter reaching 0, the PWM channel outputs

(PP0-PP4) cannot keep the state which is set by PWMLVL bit.  





 

None.